[PATCH 0/4] mtd: spi-nor: micron-st: add die erase for micron spi nor chip

[PATCH 0/4] mtd: spi-nor: micron-st: add die erase for micron spi nor chip

[Haibo Chen]

mt35xu02gcba, mt35xu01gbba and mt35xu512aba are similar, but with
different number of dies. According to the datasheet:
https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
these chips all support die erase command, but do not support chip
erase. So change the drivers accordingly.
Also add mt35xu01gbba support here, test this chip on imx95-19x19-evk
board, it works under 200MHz at 8D-8D-8D mode.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
Haibo Chen (4):
      mtd: spi-nor: micron-st: rename the die_late_init functions
      mtd: spi-nor: micron-st: add die erase for mt35xu512aba
      mtd: spi-nor: micron-st: add mt35xu01gbba support
      mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

 drivers/mtd/spi-nor/micron-st.c | 114 +++++++++++++++++++++++++++-------------
 1 file changed, 77 insertions(+), 37 deletions(-)
---
base-commit: 9c0826a5d9aa4d52206dd89976858457a2a8a7ed
change-id: 20251107-nor-84fe07ec3363

Best regards,
-- 
Haibo Chen <haibo.chen@nxp.com>

[PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init functions

[Haibo Chen]

st_nor_two/four_die_late_init() also suit for micron chips, so
rename to micron_st_nor_two/four_die_late_init().

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/micron-st.c | 70 ++++++++++++++++++++---------------------
 1 file changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 187239ccd549510c6e9a6eacf4ae41158287e077..92eb14ca76c57f29ece1edb3fe652c56d1c2888f 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -127,6 +127,38 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
 			micron_st_nor_octal_dtr_dis(nor);
 }
 
+static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+	params->n_dice = 4;
+
+	/*
+	 * Unfortunately the die erase opcode does not have a 4-byte opcode
+	 * correspondent for these flashes. The SFDP 4BAIT table fails to
+	 * consider the die erase too. We're forced to enter in the 4 byte
+	 * address mode in order to benefit of the die erase.
+	 */
+	return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
+static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+	params->n_dice = 2;
+
+	/*
+	 * Unfortunately the die erase opcode does not have a 4-byte opcode
+	 * correspondent for these flashes. The SFDP 4BAIT table fails to
+	 * consider the die erase too. We're forced to enter in the 4 byte
+	 * address mode in order to benefit of the die erase.
+	 */
+	return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
 static void mt35xu512aba_default_init(struct spi_nor *nor)
 {
 	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
@@ -193,48 +225,16 @@ static const struct spi_nor_fixups mt25qu512a_fixups = {
 	.post_bfpt = mt25qu512a_post_bfpt_fixup,
 };
 
-static int st_nor_four_die_late_init(struct spi_nor *nor)
-{
-	struct spi_nor_flash_parameter *params = nor->params;
-
-	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
-	params->n_dice = 4;
-
-	/*
-	 * Unfortunately the die erase opcode does not have a 4-byte opcode
-	 * correspondent for these flashes. The SFDP 4BAIT table fails to
-	 * consider the die erase too. We're forced to enter in the 4 byte
-	 * address mode in order to benefit of the die erase.
-	 */
-	return spi_nor_set_4byte_addr_mode(nor, true);
-}
-
-static int st_nor_two_die_late_init(struct spi_nor *nor)
-{
-	struct spi_nor_flash_parameter *params = nor->params;
-
-	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
-	params->n_dice = 2;
-
-	/*
-	 * Unfortunately the die erase opcode does not have a 4-byte opcode
-	 * correspondent for these flashes. The SFDP 4BAIT table fails to
-	 * consider the die erase too. We're forced to enter in the 4 byte
-	 * address mode in order to benefit of the die erase.
-	 */
-	return spi_nor_set_4byte_addr_mode(nor, true);
-}
-
 static const struct spi_nor_fixups n25q00_fixups = {
-	.late_init = st_nor_four_die_late_init,
+	.late_init = micron_st_nor_four_die_late_init,
 };
 
 static const struct spi_nor_fixups mt25q01_fixups = {
-	.late_init = st_nor_two_die_late_init,
+	.late_init = micron_st_nor_two_die_late_init,
 };
 
 static const struct spi_nor_fixups mt25q02_fixups = {
-	.late_init = st_nor_four_die_late_init,
+	.late_init = micron_st_nor_four_die_late_init,
 };
 
 static const struct flash_info st_nor_parts[] = {

-- 
2.34.1

[PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba

[Haibo Chen]

mt35xu512aba do not support chip erase command, and it contains one
die, and only support die erase.

Unfortunately the die erase opcode does not have a 4-byte opcode,
here forced to enter in the 4 byte address mode in order to benefit
of the die erase.

Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/micron-st.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 92eb14ca76c57f29ece1edb3fe652c56d1c2888f..89cd146095584ddebdd258a186f6398b420e5800 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -159,6 +159,22 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
 	return spi_nor_set_4byte_addr_mode(nor, true);
 }
 
+static int micron_st_nor_one_die_late_init(struct spi_nor *nor)
+{
+	struct spi_nor_flash_parameter *params = nor->params;
+
+	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
+	params->n_dice = 1;
+
+	/*
+	 * Unfortunately the die erase opcode does not have a 4-byte opcode
+	 * correspondent for these flashes. The SFDP 4BAIT table fails to
+	 * consider the die erase too. We're forced to enter in the 4 byte
+	 * address mode in order to benefit of the die erase.
+	 */
+	return spi_nor_set_4byte_addr_mode(nor, true);
+}
+
 static void mt35xu512aba_default_init(struct spi_nor *nor)
 {
 	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
@@ -189,6 +205,7 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
 static const struct spi_nor_fixups mt35xu512aba_fixups = {
 	.default_init = mt35xu512aba_default_init,
 	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
+	.late_init = micron_st_nor_one_die_late_init,
 };
 
 static const struct flash_info micron_nor_parts[] = {

-- 
2.34.1

[PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support

[Haibo Chen]

mt35xu01gbba is similar with mt35xu512aba, but with two dies.
SFDP contain the wrong size, so define the size dierctly in
the flash info. And it also support 8D-8D-8D mode, but SFDP
lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.

Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

---
1) This mt35xu01gbba is populated on the imx95-19x19-evk board, was
   tested at 200MHz using nxp,imx95-fspi SPI controller.
2) root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partname
   mt35xu01gbba
   root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id
   2c5b1b
   root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer
   micron
   root@imx95evk:~# hexdump -Cv /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
   00000000  53 46 44 50 0a 01 03 ff  00 08 01 17 30 00 00 ff  |SFDP........0...|
   00000010  84 00 01 02 90 00 00 ff  05 01 01 06 a0 00 00 ff  |................|
   00000020  0a 00 01 08 b0 00 00 ff  ff ff ff ff ff ff ff ff  |................|
   00000030  e5 20 8a ff ff ff ff 3f  00 00 00 00 00 00 00 00  |. .....?........|
   00000040  ee ff ff ff ff ff 00 00  ff ff 00 00 0c 20 11 d8  |............. ..|
   00000050  0f 52 00 00 39 61 99 00  87 8e 03 d3 ac a1 27 3d  |.R..9a........'=|
   00000060  7a 75 7a 75 fb bd d5 5c  00 00 70 ff 81 50 f8 a1  |zuzu...\..p..P..|
   00000070  2f cb 27 8b 00 00 04 01  00 06 01 00 ff ff ff 8e  |/.'.............|
   00000080  00 00 00 00 00 00 00 00  00 00 00 00 ff ff ff ff  |................|
   00000090  43 0e ff ff 21 dc 5c ff  ff ff ff ff ff ff ff ff  |C...!.\.........|
   000000a0  00 0b 80 9e b1 81 b5 85  00 f0 ff 9f 00 0a 00 00  |................|
   000000b0  00 0a 1a 88 10 00 00 00  ff ff ff ff ff ff ff ff  |................|
   000000c0  00 00 06 01 00 00 00 00  14 01 81 03 00 00 00 00  |................|
   000000d0
   root@imx95evk:~# sha256sum /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
   3848f0bd2436d7ca1373cee33f90e09d6479d0f4dc4bfd19f6a082d9e0039495  /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
3) root@imx95evk:~# cat /sys/kernel/debug/spi-nor/spi1.0/capabilities
   Supported read modes by the flash
    1S-1S-1S
     opcode        0x13
     mode cycles   0
     dummy cycles  0
    1S-1S-8S
     opcode        0x7c
     mode cycles   1
     dummy cycles  7
    1S-8S-8S
     opcode        0xcc
     mode cycles   1
     dummy cycles  15
    8D-8D-8D
     opcode        0xfd
     mode cycles   0
     dummy cycles  20

   Supported page program modes by the flash
    1S-1S-1S
     opcode        0x12
    8D-8D-8D
     opcode        0x12

   root@imx95evk:~# cat /sys/kernel/debug/spi-nor/spi1.0/params
   name            mt35xu01gbba
   id              2c 5b 1b 10 41 00
   size            128 MiB
   write size      1
   page size       256
   address nbytes  4
   flags           4B_OPCODES | HAS_4BAIT | HAS_LOCK | IO_MODE_EN_VOLATILE | SOFT_RESET

   opcodes
    read           0xfd
      dummy cycles  20
    erase          0xdc
    program        0x12
    8D extension   repeat

   protocols
    read           8D-8D-8D
    write          8D-8D-8D
    register       8D-8D-8D

   erase commands
     21 (4.00 KiB) [1]
     5c (32.0 KiB) [2]
     dc (128 KiB) [3]
     c4 (128 MiB)

   sector map
     region (in hex)   | erase mask | overlaid
     ------------------+------------+----------
     00000000-07ffffff |     [   3] | no
4) root@imx95evk:~# dd if=/dev/urandom of=./spi_test bs=1M count=2
   2+0 records in
   2+0 records out
   2097152 bytes (2.1 MB, 2.0 MiB) copied, 0.0207974 s, 101 MB/s
   root@imx95evk:~# mtd_debug erase /dev/mtd0 0 2097152
   Erased 2097152 bytes from address 0x00000000 in flash
   root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
   Copied 2097152 bytes from address 0x00000000 in flash to spi_read
   root@imx95evk:~# hexdump spi_read
   0000000 ffff ffff ffff ffff ffff ffff ffff ffff
   *
   0200000
   root@imx95evk:~# sha256sum spi_read
   4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  spi_read
   root@imx95evk:~# mtd_debug write /dev/mtd0 0 2097152 spi_test
   Copied 2097152 bytes from spi_test to address 0x00000000 in flash
   root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
   Copied 2097152 bytes from address 0x00000000 in flash to spi_read
   root@imx95evk:~# sha256sum spi*
   57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205  spi_read
   57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205  spi_test
   root@imx95evk:~# mtd_debug erase /dev/mtd0 0 2097152
   Erased 2097152 bytes from address 0x00000000 in flash
   root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
   Copied 2097152 bytes from address 0x00000000 in flash to spi_read
   root@imx95evk:~# sha256sum spi*
   4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5  spi_read
   57300768c1271d4588b850dcbf4e1400f287f09b2d515eda610890456695b205  spi_test
   root@imx95evk:~# mtd_debug info /dev/mtd0
   mtd.type = MTD_NORFLASH
   mtd.flags = MTD_CAP_NORFLASH
   mtd.size = 134217728 (128M)
   mtd.erasesize = 131072 (128K)
   mtd.writesize = 1
   mtd.oobsize = 0
   regions = 0
   root@imx95evk:~# flash_erase /dev/mtd0 0 0
   Erasing 131072 Kibyte @ 0 -- 100 % complete
   root@imx95evk:~# mtd_debug read /dev/mtd0 0 2097152 spi_read
   Copied 2097152 bytes from address 0x00000000 in flash to spi_read
   root@imx95evk:~# hexdump spi_read
   0000000 ffff ffff ffff ffff ffff ffff ffff ffff
   *
   0200000
---
 drivers/mtd/spi-nor/micron-st.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 89cd146095584ddebdd258a186f6398b420e5800..f724313f4dd3720908968c670e8d3d58f41c099c 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -208,6 +208,12 @@ static const struct spi_nor_fixups mt35xu512aba_fixups = {
 	.late_init = micron_st_nor_one_die_late_init,
 };
 
+static const struct spi_nor_fixups mt35xu01gbba_fixups = {
+	.default_init = mt35xu512aba_default_init,
+	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
+	.late_init = micron_st_nor_two_die_late_init,
+};
+
 static const struct flash_info micron_nor_parts[] = {
 	{
 		.id = SNOR_ID(0x2c, 0x5b, 0x1a),
@@ -219,6 +225,16 @@ static const struct flash_info micron_nor_parts[] = {
 		.mfr_flags = USE_FSR,
 		.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
 		.fixups = &mt35xu512aba_fixups,
+	}, {
+		.id = SNOR_ID(0x2c, 0x5b, 0x1b),
+		.name = "mt35xu01gbba",
+		.sector_size = SZ_128K,
+		.size = SZ_128M,
+		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
+				 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,
+		.mfr_flags = USE_FSR,
+		.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
+		.fixups = &mt35xu01gbba_fixups,
 	}, {
 		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
 		.name = "mt35xu02g",

-- 
2.34.1

[PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

[Haibo Chen]

mt35xu02gcba is similar with mt35xu01gbba and mt35xu512aba, but with
four dies inside. And it also support 8D-8D-8D mode, but SFDP lack
SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.

Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
---
 drivers/mtd/spi-nor/micron-st.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index f724313f4dd3720908968c670e8d3d58f41c099c..b36174436b7aa0f7768dbe48e4ad4927c08a3d6d 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -214,6 +214,12 @@ static const struct spi_nor_fixups mt35xu01gbba_fixups = {
 	.late_init = micron_st_nor_two_die_late_init,
 };
 
+static const struct spi_nor_fixups mt35xu02gcba_fixups = {
+	.default_init = mt35xu512aba_default_init,
+	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
+	.late_init = micron_st_nor_four_die_late_init,
+};
+
 static const struct flash_info micron_nor_parts[] = {
 	{
 		.id = SNOR_ID(0x2c, 0x5b, 0x1a),
@@ -237,12 +243,13 @@ static const struct flash_info micron_nor_parts[] = {
 		.fixups = &mt35xu01gbba_fixups,
 	}, {
 		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
-		.name = "mt35xu02g",
+		.name = "mt35xu02gcba",
 		.sector_size = SZ_128K,
 		.size = SZ_256M,
 		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
 		.mfr_flags = USE_FSR,
-		.fixup_flags = SPI_NOR_4B_OPCODES,
+		.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,
+		.fixups = &mt35xu02gcba_fixups,
 	},
 };
 

-- 
2.34.1

Re: [PATCH 1/4] mtd: spi-nor: micron-st: rename the die_late_init functions

[Tudor Ambarus]

On 11/10/25 6:02 AM, Haibo Chen wrote:
> st_nor_two/four_die_late_init() also suit for micron chips, so
> rename to micron_st_nor_two/four_die_late_init().
> 
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
>  drivers/mtd/spi-nor/micron-st.c | 70 ++++++++++++++++++++---------------------
>  1 file changed, 35 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 187239ccd549510c6e9a6eacf4ae41158287e077..92eb14ca76c57f29ece1edb3fe652c56d1c2888f 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -127,6 +127,38 @@ static int micron_st_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
>  			micron_st_nor_octal_dtr_dis(nor);
>  }
>  
> +static int micron_st_nor_four_die_late_init(struct spi_nor *nor)
> +{
> +	struct spi_nor_flash_parameter *params = nor->params;
> +
> +	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> +	params->n_dice = 4;
> +
> +	/*
> +	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> +	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> +	 * consider the die erase too. We're forced to enter in the 4 byte
> +	 * address mode in order to benefit of the die erase.
> +	 */
> +	return spi_nor_set_4byte_addr_mode(nor, true);
> +}
> +
> +static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
> +{
> +	struct spi_nor_flash_parameter *params = nor->params;
> +
> +	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> +	params->n_dice = 2;
> +
> +	/*
> +	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> +	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> +	 * consider the die erase too. We're forced to enter in the 4 byte
> +	 * address mode in order to benefit of the die erase.
> +	 */
> +	return spi_nor_set_4byte_addr_mode(nor, true);
> +}

I see you also moved the methods a bit up, maybe to have all micron_st methods
in one place. Specify this in the commit message to spare reviewers of checking
bit-to-bit exact move.

With that:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>

> +
>  static void mt35xu512aba_default_init(struct spi_nor *nor)
>  {
>  	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
> @@ -193,48 +225,16 @@ static const struct spi_nor_fixups mt25qu512a_fixups = {
>  	.post_bfpt = mt25qu512a_post_bfpt_fixup,
>  };
>  
> -static int st_nor_four_die_late_init(struct spi_nor *nor)
> -{
> -	struct spi_nor_flash_parameter *params = nor->params;
> -
> -	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> -	params->n_dice = 4;
> -
> -	/*
> -	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> -	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> -	 * consider the die erase too. We're forced to enter in the 4 byte
> -	 * address mode in order to benefit of the die erase.
> -	 */
> -	return spi_nor_set_4byte_addr_mode(nor, true);
> -}
> -
> -static int st_nor_two_die_late_init(struct spi_nor *nor)
> -{
> -	struct spi_nor_flash_parameter *params = nor->params;
> -
> -	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> -	params->n_dice = 2;
> -
> -	/*
> -	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> -	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> -	 * consider the die erase too. We're forced to enter in the 4 byte
> -	 * address mode in order to benefit of the die erase.
> -	 */
> -	return spi_nor_set_4byte_addr_mode(nor, true);
> -}
> -
>  static const struct spi_nor_fixups n25q00_fixups = {
> -	.late_init = st_nor_four_die_late_init,
> +	.late_init = micron_st_nor_four_die_late_init,
>  };
>  
>  static const struct spi_nor_fixups mt25q01_fixups = {
> -	.late_init = st_nor_two_die_late_init,
> +	.late_init = micron_st_nor_two_die_late_init,
>  };
>  
>  static const struct spi_nor_fixups mt25q02_fixups = {
> -	.late_init = st_nor_four_die_late_init,
> +	.late_init = micron_st_nor_four_die_late_init,
>  };
>  
>  static const struct flash_info st_nor_parts[] = {
> 

Re: [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba

[Tudor Ambarus]

On 11/10/25 6:02 AM, Haibo Chen wrote:
> mt35xu512aba do not support chip erase command, and it contains one
> die, and only support die erase.

does this need a fixes tag then? With that:
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>> 
> Unfortunately the die erase opcode does not have a 4-byte opcode,
> here forced to enter in the 4 byte address mode in order to benefit
> of the die erase.
> 
> Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---

Also, would you please help us with SFDP dumps, as you did in the next patches?
It helps ups keep a database and update flashes to get rid of the non SFDP data.

Thanks!

>  drivers/mtd/spi-nor/micron-st.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index 92eb14ca76c57f29ece1edb3fe652c56d1c2888f..89cd146095584ddebdd258a186f6398b420e5800 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -159,6 +159,22 @@ static int micron_st_nor_two_die_late_init(struct spi_nor *nor)
>  	return spi_nor_set_4byte_addr_mode(nor, true);
>  }
>  
> +static int micron_st_nor_one_die_late_init(struct spi_nor *nor)
> +{
> +	struct spi_nor_flash_parameter *params = nor->params;
> +
> +	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> +	params->n_dice = 1;
> +
> +	/*
> +	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> +	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> +	 * consider the die erase too. We're forced to enter in the 4 byte
> +	 * address mode in order to benefit of the die erase.
> +	 */
> +	return spi_nor_set_4byte_addr_mode(nor, true);
> +}
> +
>  static void mt35xu512aba_default_init(struct spi_nor *nor)
>  {
>  	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr;
> @@ -189,6 +205,7 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
>  static const struct spi_nor_fixups mt35xu512aba_fixups = {
>  	.default_init = mt35xu512aba_default_init,
>  	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
> +	.late_init = micron_st_nor_one_die_late_init,
>  };
>  
>  static const struct flash_info micron_nor_parts[] = {
> 

Re: [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support

[Tudor Ambarus]

On 11/10/25 6:02 AM, Haibo Chen wrote:
> mt35xu01gbba is similar with mt35xu512aba, but with two dies.
> SFDP contain the wrong size, so define the size dierctly in
> the flash info. And it also support 8D-8D-8D mode, but SFDP
> lack SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
> 
> Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> 
> ---
> 1) This mt35xu01gbba is populated on the imx95-19x19-evk board, was
>    tested at 200MHz using nxp,imx95-fspi SPI controller.
> 2) root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partname
>    mt35xu01gbba
>    root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id
>    2c5b1b
>    root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer
>    micron
>    root@imx95evk:~# hexdump -Cv /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
>    00000000  53 46 44 50 0a 01 03 ff  00 08 01 17 30 00 00 ff  |SFDP........0...|
>    00000010  84 00 01 02 90 00 00 ff  05 01 01 06 a0 00 00 ff  |................|
>    00000020  0a 00 01 08 b0 00 00 ff  ff ff ff ff ff ff ff ff  |................|
>    00000030  e5 20 8a ff ff ff ff 3f  00 00 00 00 00 00 00 00  |. .....?........|
>    00000040  ee ff ff ff ff ff 00 00  ff ff 00 00 0c 20 11 d8  |............. ..|
>    00000050  0f 52 00 00 39 61 99 00  87 8e 03 d3 ac a1 27 3d  |.R..9a........'=|
>    00000060  7a 75 7a 75 fb bd d5 5c  00 00 70 ff 81 50 f8 a1  |zuzu...\..p..P..|
>    00000070  2f cb 27 8b 00 00 04 01  00 06 01 00 ff ff ff 8e  |/.'.............|
>    00000080  00 00 00 00 00 00 00 00  00 00 00 00 ff ff ff ff  |................|
>    00000090  43 0e ff ff 21 dc 5c ff  ff ff ff ff ff ff ff ff  |C...!.\.........|
>    000000a0  00 0b 80 9e b1 81 b5 85  00 f0 ff 9f 00 0a 00 00  |................|
>    000000b0  00 0a 1a 88 10 00 00 00  ff ff ff ff ff ff ff ff  |................|
>    000000c0  00 00 06 01 00 00 00 00  14 01 81 03 00 00 00 00  |................|
>    000000d0

you have SFDP here

cut

> +	}, {
> +		.id = SNOR_ID(0x2c, 0x5b, 0x1b),
> +		.name = "mt35xu01gbba",

drop the name field and add it as a comment. See recent flash additions commits.> +		.sector_size = SZ_128K,
> +		.size = SZ_128M,

drop these, SFDP shall handle them.

> +		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
> +				 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,

Drop this line, let SFDP handle it

> +		.mfr_flags = USE_FSR,
> +		.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,

can we drop SPI_NOR_4B_OPCODES?

> +		.fixups = &mt35xu01gbba_fixups,
>  	}, {
>  		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
>  		.name = "mt35xu02g",
> 

Re: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

[Tudor Ambarus]

On 11/10/25 6:02 AM, Haibo Chen wrote:
> mt35xu02gcba is similar with mt35xu01gbba and mt35xu512aba, but with
> four dies inside. And it also support 8D-8D-8D mode, but SFDP lack
> SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
> 
> Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---

please dump the SFDP data for every flash that you touch, it helps
us with the sfdp database

>  drivers/mtd/spi-nor/micron-st.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
> index f724313f4dd3720908968c670e8d3d58f41c099c..b36174436b7aa0f7768dbe48e4ad4927c08a3d6d 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -214,6 +214,12 @@ static const struct spi_nor_fixups mt35xu01gbba_fixups = {
>  	.late_init = micron_st_nor_two_die_late_init,
>  };
>  
> +static const struct spi_nor_fixups mt35xu02gcba_fixups = {
> +	.default_init = mt35xu512aba_default_init,
> +	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
> +	.late_init = micron_st_nor_four_die_late_init,
> +};
> +
>  static const struct flash_info micron_nor_parts[] = {
>  	{
>  		.id = SNOR_ID(0x2c, 0x5b, 0x1a),
> @@ -237,12 +243,13 @@ static const struct flash_info micron_nor_parts[] = {
>  		.fixups = &mt35xu01gbba_fixups,
>  	}, {
>  		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
> -		.name = "mt35xu02g",
> +		.name = "mt35xu02gcba",

we don't care about the name, drop the name and add it as a comment.

>  		.sector_size = SZ_128K,
>  		.size = SZ_256M,
>  		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
>  		.mfr_flags = USE_FSR,
> -		.fixup_flags = SPI_NOR_4B_OPCODES,
> +		.fixup_flags = SPI_NOR_4B_OPCODES | SPI_NOR_IO_MODE_EN_VOLATILE,

Whenever you can, remove the non-sfdp static data and rely on the SFDP
driver to handle it. Can you please drop sector_size, no_sfdp_flags and
SPI_NOR_4B_OPCODES?

Then do the testing and sysfs/debugfs dumps to prove the flash works okay.
Thanks!
ta> +		.fixups = &mt35xu02gcba_fixups,
>  	},
>  };
>  
> 

RE: [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for mt35xu512aba

[Bough Chen]

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> Sent: 2025年11月10日 14:39
> To: Bough Chen <haibo.chen@nxp.com>; Pratyush Yadav
> <pratyush@kernel.org>; Michael Walle <mwalle@kernel.org>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>
> Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> imx@lists.linux.dev
> Subject: Re: [PATCH 2/4] mtd: spi-nor: micron-st: add die erase for
> mt35xu512aba
> 
> 
> 
> On 11/10/25 6:02 AM, Haibo Chen wrote:
> > mt35xu512aba do not support chip erase command, and it contains one
> > die, and only support die erase.
> 
> does this need a fixes tag then? With that:
> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>>
> > Unfortunately the die erase opcode does not have a 4-byte opcode, here
> > forced to enter in the 4 byte address mode in order to benefit of the
> > die erase.
> >
> > Link:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> >
> sheet.octopart.com%2FMT35XU02GCBA1G12-0AAT-Micron-datasheet-138896
> 808.
> >
> pdf&data=05%7C02%7Chaibo.chen%40nxp.com%7C2632ec31f3424748f8a308d
> e2023
> >
> c973%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C6389835352669
> 00290%7
> >
> CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlA
> >
> iOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=H
> 0Boi
> > thmOc0vuK6MNfCYHCgS8fPONWqzPi%2Fi5gFlcuA%3D&reserved=0
> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> > ---
> 
> Also, would you please help us with SFDP dumps, as you did in the next patches?
> It helps ups keep a database and update flashes to get rid of the non SFDP data.

Okay, will add in next version.

Regards
Haibo Chen
> 
> Thanks!
> 
> >  drivers/mtd/spi-nor/micron-st.c | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/micron-st.c
> > b/drivers/mtd/spi-nor/micron-st.c index
> >
> 92eb14ca76c57f29ece1edb3fe652c56d1c2888f..89cd146095584ddebdd258a18
> 6f6
> > 398b420e5800 100644
> > --- a/drivers/mtd/spi-nor/micron-st.c
> > +++ b/drivers/mtd/spi-nor/micron-st.c
> > @@ -159,6 +159,22 @@ static int micron_st_nor_two_die_late_init(struct
> spi_nor *nor)
> >  	return spi_nor_set_4byte_addr_mode(nor, true);  }
> >
> > +static int micron_st_nor_one_die_late_init(struct spi_nor *nor) {
> > +	struct spi_nor_flash_parameter *params = nor->params;
> > +
> > +	params->die_erase_opcode = SPINOR_OP_MT_DIE_ERASE;
> > +	params->n_dice = 1;
> > +
> > +	/*
> > +	 * Unfortunately the die erase opcode does not have a 4-byte opcode
> > +	 * correspondent for these flashes. The SFDP 4BAIT table fails to
> > +	 * consider the die erase too. We're forced to enter in the 4 byte
> > +	 * address mode in order to benefit of the die erase.
> > +	 */
> > +	return spi_nor_set_4byte_addr_mode(nor, true); }
> > +
> >  static void mt35xu512aba_default_init(struct spi_nor *nor)  {
> >  	nor->params->set_octal_dtr = micron_st_nor_set_octal_dtr; @@ -189,6
> > +205,7 @@ static int mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
> > static const struct spi_nor_fixups mt35xu512aba_fixups = {
> >  	.default_init = mt35xu512aba_default_init,
> >  	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
> > +	.late_init = micron_st_nor_one_die_late_init,
> >  };
> >
> >  static const struct flash_info micron_nor_parts[] = {
> >

RE: [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support

[Bough Chen]

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> Sent: 2025年11月10日 14:42
> To: Bough Chen <haibo.chen@nxp.com>; Pratyush Yadav
> <pratyush@kernel.org>; Michael Walle <mwalle@kernel.org>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>
> Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> imx@lists.linux.dev
> Subject: Re: [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support
> 
> 
> 
> On 11/10/25 6:02 AM, Haibo Chen wrote:
> > mt35xu01gbba is similar with mt35xu512aba, but with two dies.
> > SFDP contain the wrong size, so define the size dierctly in the flash
> > info. And it also support 8D-8D-8D mode, but SFDP lack
> > SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
> >
> > Link:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> >
> sheet.octopart.com%2FMT35XU02GCBA1G12-0AAT-Micron-datasheet-138896
> 808.
> >
> pdf&data=05%7C02%7Chaibo.chen%40nxp.com%7Cca28ca59a1734e70621908
> de2024
> >
> 464e%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C6389835373320
> 21937%7
> >
> CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlA
> >
> iOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=6j
> nlg
> > lV4H5w%2BIb3Ua3aNOClElU0MfICnqWYvjWnRCEA%3D&reserved=0
> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> >
> > ---
> > 1) This mt35xu01gbba is populated on the imx95-19x19-evk board, was
> >    tested at 200MHz using nxp,imx95-fspi SPI controller.
> > 2) root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partname
> >    mt35xu01gbba
> >    root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec_id
> >    2c5b1b
> >    root@imx95evk:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manufacturer
> >    micron
> >    root@imx95evk:~# hexdump -Cv /sys/bus/spi/devices/spi1.0/spi-nor/sfdp
> >    00000000  53 46 44 50 0a 01 03 ff  00 08 01 17 30 00 00 ff
> |SFDP........0...|
> >    00000010  84 00 01 02 90 00 00 ff  05 01 01 06 a0 00 00 ff
> |................|
> >    00000020  0a 00 01 08 b0 00 00 ff  ff ff ff ff ff ff ff ff  |................|
> >    00000030  e5 20 8a ff ff ff ff 3f  00 00 00 00 00 00 00 00  |. .....?........|
> >    00000040  ee ff ff ff ff ff 00 00  ff ff 00 00 0c 20 11 d8  |............. ..|
> >    00000050  0f 52 00 00 39 61 99 00  87 8e 03 d3 ac a1 27 3d
> |.R..9a........'=|
> >    00000060  7a 75 7a 75 fb bd d5 5c  00 00 70 ff 81 50 f8 a1
> |zuzu...\..p..P..|
> >    00000070  2f cb 27 8b 00 00 04 01  00 06 01 00 ff ff ff 8e
> |/.'.............|
> >    00000080  00 00 00 00 00 00 00 00  00 00 00 00 ff ff ff ff
> |................|
> >    00000090  43 0e ff ff 21 dc 5c ff  ff ff ff ff ff ff ff ff  |C...!.\.........|
> >    000000a0  00 0b 80 9e b1 81 b5 85  00 f0 ff 9f 00 0a 00 00
> |................|
> >    000000b0  00 0a 1a 88 10 00 00 00  ff ff ff ff ff ff ff ff  |................|
> >    000000c0  00 00 06 01 00 00 00 00  14 01 81 03 00 00 00 00
> |................|
> >    000000d0
> 
> you have SFDP here
> 
> cut
> 
> > +	}, {
> > +		.id = SNOR_ID(0x2c, 0x5b, 0x1b),
> > +		.name = "mt35xu01gbba",
> 
> drop the name field and add it as a comment. See recent flash additions
> commits.> +		.sector_size = SZ_128K,
> > +		.size = SZ_128M,

I did consider to remove the size and other flags since SFDP can handle that, but if remove the .size here.
Micron spi-nor do not have a chance to execute

params->set_octal_dtr = micron_st_nor_set_octal_dtr;

because in micron-st, params->set_octal_dtr is defined in flash_info->fixups-> default_init.
And flash_info->fixups-> default_init can only be called in spi_nor_init_params_deprecated-> spi_nor_manufacturer_init_params
If no .size define in flash_info, spi_nor_needs_sfdp() will return true, no chance to call spi_nor_init_params_deprecated.

If need to remove the .size here, seems to move the params->set_octal_dtr to spi_nor_manufacturer-> fixups-> late_init or flash_info->fixups->late_init.

I notice macronix already did like that, I will add this change in the next version.

Regards
Haibo Chen
> 
> drop these, SFDP shall handle them.
> 
> > +		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ |
> > +				 SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP,
> 
> Drop this line, let SFDP handle it
> 
> > +		.mfr_flags = USE_FSR,
> > +		.fixup_flags = SPI_NOR_4B_OPCODES |
> SPI_NOR_IO_MODE_EN_VOLATILE,
> 
> can we drop SPI_NOR_4B_OPCODES?
> 
> > +		.fixups = &mt35xu01gbba_fixups,
> >  	}, {
> >  		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
> >  		.name = "mt35xu02g",
> >

RE: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

[Bough Chen]

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> Sent: 2025年11月10日 14:46
> To: Bough Chen <haibo.chen@nxp.com>; Pratyush Yadav
> <pratyush@kernel.org>; Michael Walle <mwalle@kernel.org>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>
> Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> imx@lists.linux.dev
> Subject: Re: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die
> erase for mt35xu02gcba
> 
> 
> 
> On 11/10/25 6:02 AM, Haibo Chen wrote:
> > mt35xu02gcba is similar with mt35xu01gbba and mt35xu512aba, but with
> > four dies inside. And it also support 8D-8D-8D mode, but SFDP lack
> > SNOR_F_IO_MODE_EN_VOLATILE, so add this fixup flags here.
> >
> > Link:
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdata
> >
> sheet.octopart.com%2FMT35XU02GCBA1G12-0AAT-Micron-datasheet-138896
> 808.
> >
> pdf&data=05%7C02%7Chaibo.chen%40nxp.com%7Cc6a4b5f4f56f4ca716d208d
> e2024
> >
> d0a0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C6389835396808
> 11304%7
> >
> CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlA
> >
> iOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=6
> Dqhh
> > hlIzdxftTmQzmj%2BcomjZWxWOqpDWP5%2B4NUGCK0%3D&reserved=0
> > Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> > ---
> 
> please dump the SFDP data for every flash that you touch, it helps us with the
> sfdp database

Hi Tudor,

I do not have this mt35xu02gcba on hand, I only has mt35xu512aba and mt35xu01gbba.
I touch this chip because I notice these three chips share one datasheet, and seems only
has different number of dies.

So should I drop this patch?

Regards
Haibo Chen
> 
> >  drivers/mtd/spi-nor/micron-st.c | 11 +++++++++--
> >  1 file changed, 9 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/micron-st.c
> > b/drivers/mtd/spi-nor/micron-st.c index
> >
> f724313f4dd3720908968c670e8d3d58f41c099c..b36174436b7aa0f7768dbe48e
> 4ad
> > 4927c08a3d6d 100644
> > --- a/drivers/mtd/spi-nor/micron-st.c
> > +++ b/drivers/mtd/spi-nor/micron-st.c
> > @@ -214,6 +214,12 @@ static const struct spi_nor_fixups
> mt35xu01gbba_fixups = {
> >  	.late_init = micron_st_nor_two_die_late_init,  };
> >
> > +static const struct spi_nor_fixups mt35xu02gcba_fixups = {
> > +	.default_init = mt35xu512aba_default_init,
> > +	.post_sfdp = mt35xu512aba_post_sfdp_fixup,
> > +	.late_init = micron_st_nor_four_die_late_init, };
> > +
> >  static const struct flash_info micron_nor_parts[] = {
> >  	{
> >  		.id = SNOR_ID(0x2c, 0x5b, 0x1a),
> > @@ -237,12 +243,13 @@ static const struct flash_info micron_nor_parts[] = {
> >  		.fixups = &mt35xu01gbba_fixups,
> >  	}, {
> >  		.id = SNOR_ID(0x2c, 0x5b, 0x1c),
> > -		.name = "mt35xu02g",
> > +		.name = "mt35xu02gcba",
> 
> we don't care about the name, drop the name and add it as a comment.
> 
> >  		.sector_size = SZ_128K,
> >  		.size = SZ_256M,
> >  		.no_sfdp_flags = SECT_4K | SPI_NOR_OCTAL_READ,
> >  		.mfr_flags = USE_FSR,
> > -		.fixup_flags = SPI_NOR_4B_OPCODES,
> > +		.fixup_flags = SPI_NOR_4B_OPCODES |
> SPI_NOR_IO_MODE_EN_VOLATILE,
> 
> Whenever you can, remove the non-sfdp static data and rely on the SFDP driver
> to handle it. Can you please drop sector_size, no_sfdp_flags and
> SPI_NOR_4B_OPCODES?
> 
> Then do the testing and sysfs/debugfs dumps to prove the flash works okay.
> Thanks!
> ta> +		.fixups = &mt35xu02gcba_fixups,
> >  	},
> >  };
> >
> >

Re: [PATCH 3/4] mtd: spi-nor: micron-st: add mt35xu01gbba support

[Tudor Ambarus]

did you use html format when replying? Use plaintext, please.

On 11/11/25 9:54 AM, Bough Chen wrote:
>>> +		.size = SZ_128M,
> I did consider to remove the size and other flags since SFDP can handle that, but if remove the .size here.
> Micron spi-nor do not have a chance to execute
> 
> params->set_octal_dtr = micron_st_nor_set_octal_dtr;
> 
> because in micron-st, params->set_octal_dtr is defined in flash_info->fixups-> default_init.
> And flash_info->fixups-> default_init can only be called in spi_nor_init_params_deprecated-> spi_nor_manufacturer_init_params
> If no .size define in flash_info, spi_nor_needs_sfdp() will return true, no chance to call spi_nor_init_params_deprecated.
> 
> If need to remove the .size here, seems to move the params->set_octal_dtr to spi_nor_manufacturer-> fixups-> late_init or flash_info->fixups->late_init.
> 
> I notice macronix already did like that, I will add this change in the next version.

Yes, move that to late_int(). We'd like to remove default_init()
if possible.

Cheers,
ta

Re: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

[Tudor Ambarus]

On 11/11/25 10:00 AM, Bough Chen wrote:
>> please dump the SFDP data for every flash that you touch, it helps us with the
>> sfdp database
> Hi Tudor,
> 
> I do not have this mt35xu02gcba on hand, I only has mt35xu512aba and mt35xu01gbba.
> I touch this chip because I notice these three chips share one datasheet, and seems only
> has different number of dies.
> 
> So should I drop this patch?

Ideally we don't change functionality for flashes if we can't test them.
If you feel this flash entry does not work okay, which seems it's the
case based on your previous patches, then just add a comment above this
flash entry and tell what should be changed. Then if someone cares and
have the flash, can do the changes and fix it as you suggest. Does this
sound like a reasonable compromise?

Cheers,
ta

RE: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die erase for mt35xu02gcba

[Bough Chen]

> -----Original Message-----
> From: Tudor Ambarus <tudor.ambarus@linaro.org>
> Sent: 2025年11月11日 16:29
> To: Bough Chen <haibo.chen@nxp.com>; Pratyush Yadav
> <pratyush@kernel.org>; Michael Walle <mwalle@kernel.org>; Miquel Raynal
> <miquel.raynal@bootlin.com>; Richard Weinberger <richard@nod.at>; Vignesh
> Raghavendra <vigneshr@ti.com>
> Cc: linux-mtd@lists.infradead.org; linux-kernel@vger.kernel.org;
> imx@lists.linux.dev
> Subject: Re: [PATCH 4/4] mtd: spi-nor: micron-st: enable 8D-8D-8D mode and die
> erase for mt35xu02gcba
> 
> 
> 
> On 11/11/25 10:00 AM, Bough Chen wrote:
> >> please dump the SFDP data for every flash that you touch, it helps us
> >> with the sfdp database
> > Hi Tudor,
> >
> > I do not have this mt35xu02gcba on hand, I only has mt35xu512aba and
> mt35xu01gbba.
> > I touch this chip because I notice these three chips share one
> > datasheet, and seems only has different number of dies.
> >
> > So should I drop this patch?
> 
> Ideally we don't change functionality for flashes if we can't test them.
> If you feel this flash entry does not work okay, which seems it's the case based on
> your previous patches, then just add a comment above this flash entry and tell
> what should be changed. Then if someone cares and have the flash, can do the
> changes and fix it as you suggest. Does this sound like a reasonable compromise?

Okay, will add comment in next version.

Thanks for your quick reply.

Regards
Haibo Chen
> 
> Cheers,
> ta