From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Haibo Chen <haibo.chen@nxp.com>,
Pratyush Yadav <pratyush@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
imx@lists.linux.dev
Subject: Re: [PATCH v3 5/5] mtd: spi-nor: micron-st: add comment for mt35xu02gcba
Date: Wed, 12 Nov 2025 11:22:39 +0200 [thread overview]
Message-ID: <ea9d58d9-30bc-4793-a111-1df428f74e31@linaro.org> (raw)
In-Reply-To: <013215bb-3562-484f-868d-485d0da095d8@linaro.org>
On 11/12/25 11:21 AM, Tudor Ambarus wrote:
>
>
> On 11/12/25 8:48 AM, Haibo Chen wrote:
>> mt35xu02gcba is similar with mt35xu01gbba, but with four
>> dies inside. According to datasheet, it contain SFDP and
>> support 8D-8D-8D mode. Add comments here, remider to change
>> the code in future if has a chance to test on this chip.
>
> you'll need to rephrase a bit the above>
>> Link: https://datasheet.octopart.com/MT35XU02GCBA1G12-0AAT-Micron-datasheet-138896808.pdf
>> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
>> ---
>> drivers/mtd/spi-nor/micron-st.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
>> index 6d081ec176c37249e5ddb724b61bd70f68088163..cc053b4d615ade3f12068618f8355779561dce55 100644
>> --- a/drivers/mtd/spi-nor/micron-st.c
>> +++ b/drivers/mtd/spi-nor/micron-st.c
>> @@ -206,6 +206,12 @@ static const struct flash_info micron_nor_parts[] = {
>> .fixup_flags = SPI_NOR_IO_MODE_EN_VOLATILE,
>> .fixups = &mt35xu01gbba_fixups,
>> }, {
>> + /*
>> + * MT35XU02GCBA contain SFDP, so no need the size
>> + * and no_sfdp_flags here, should similar with
>
> this is expected for all the flashes that have SFDP, so no need to
> specify this again here.
>
>> + * MT35XU01GBBA, but with 4 dies. If someone can
>> + * test on this chip, can change accordingly.
>> + */
>
> How about we rephrase this to:
> The MT35XU02GCBA flash device does not support chip erase, according to
> its datasheet. It only supports die erase, which means the current driver
drop "only" as it supports sector erase as well :)
> implementation will likely need to be converted to use die erase.
> Furthermore, similar to the MT35XU01GBBA, the SPI_NOR_IO_MODE_EN_VOLATILE
> flag probably needs to be enabled.
>
> With something along the above lines you can add:
> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
>
>> .id = SNOR_ID(0x2c, 0x5b, 0x1c),
>> .name = "mt35xu02g",
>> .sector_size = SZ_128K,
>>
>
prev parent reply other threads:[~2025-11-12 9:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 6:48 [PATCH v3 0/5] mtd: spi-nor: micron-st: few clean up for micron spi nor chip Haibo Chen
2025-11-12 6:48 ` [PATCH v3 1/5] mtd: spi-nor: micron-st: rename the die_late_init functions Haibo Chen
2025-11-12 6:48 ` [PATCH v3 2/5] mtd: spi-nor: micron-st: move set_octal_dtr to late_init() Haibo Chen
2025-11-12 9:01 ` Tudor Ambarus
2025-11-12 6:48 ` [PATCH v3 3/5] mtd: spi-nor: micron-st: use SFDP of mt35xu512aba Haibo Chen
2025-11-12 9:05 ` Tudor Ambarus
2025-11-12 6:48 ` [PATCH v3 4/5] mtd: spi-nor: micron-st: add mt35xu01gbba support Haibo Chen
2025-11-12 9:07 ` Tudor Ambarus
2025-11-12 6:48 ` [PATCH v3 5/5] mtd: spi-nor: micron-st: add comment for mt35xu02gcba Haibo Chen
2025-11-12 9:21 ` Tudor Ambarus
2025-11-12 9:22 ` Tudor Ambarus [this message]
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