[v3 00/14] drm/i915/color: Enable SDR plane color pipeline
2026-06-17 10:52 UTC (16+ messages)
` [v3 01/14] drm/colorop: Add DRM_COLOROP_FIXED_MATRIX
` [v3 02/14] drm/i915/color: Add CSC on SDR plane color pipeline
` [v3 03/14] drm/i915/display: extract glk_plane_color_ctl_input_csc helper
` [v3 04/14] drm/i915/display: simplify glk_plane_color_ctl_input_csc
` [v3 05/14] drm/i915/display: Track CSC mode in intel plane state
` [v3 06/14] drm/i915/display: Program input CSC on SDR planes
` [v3 07/14] drm/i915/color: Add YCbCr limited-to-full range color block support
` [v3 08/14] drm/i915/color: Add YUV range correction to SDR plane pipeline
` [v3 09/14] drm/i915/color: Add support for 1D LUT in SDR planes
` [v3 10/14] drm/i915/color: Extract HDR pre-CSC LUT programming to helper function
` [v3 11/14] drm/i915/color: Program Pre-CSC registers for SDR
` [v3 12/14] drm/i915/color: Extract HDR post-CSC LUT programming to helper function
` [v3 13/14] drm/i915/color: Program Plane Post CSC registers for SDR planes
` [v3 14/14] drm/i915/color: Add color pipeline support "
` ✗ i915.CI.BAT: failure for drm/i915/color: Enable SDR plane color pipeline (rev3)
[PATCH v6 00/16] drm/i915/display: Add DC3CO support
2026-06-17 10:45 UTC (36+ messages)
` [PATCH v6 01/16] drm/i915/display: Remove TGL "
` [PATCH v6 02/16] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding
` [PATCH v6 03/16] drm/i915/display: Use FIELD_PREP() for DC state enable bits
` [PATCH v6 04/16] drm/i915/display: Add DC3CO DC_STATE enable/disable support
` [PATCH v6 05/16] drm/i915/display: Add HAS_DC3CO() macro
` [PATCH v6 06/16] drm/i915/display: Add DC3CO support check
` [PATCH v6 07/16] drm/i915/psr: Add psr2 deep sleep helper API
` [PATCH v6 08/16] drm/i915/display: Add DC3CO compute and set target state in commit tail
` [PATCH v6 09/16] drm/i915/display: Store DC3CO eligibility in PSR state
` [PATCH v6 10/16] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
` [PATCH v6 11/16] drm/i915/display: Enable DC3CO idle protocol in ALPM
` [PATCH v6 12/16] drm/i915/display: PSR Add delayed work to exit DC3CO
` [PATCH v6 13/16] drm/i915/display: Add helper to enable DC counter
` [PATCH v6 14/16] drm/i915/display: Add DC3CO count and residency in dmc debugfs
` [PATCH v6 15/16] drm/i915/display: Guard CMTG function calls
` [PATCH v6 16/16] drm/i915/display: Enable DC3CO DC state
` ✓ i915.CI.BAT: success for drm/i915/display: Add DC3CO support (rev6)
` ✓ i915.CI.Full: "
[2/2] drm/i915/display: Refcount for fec enable/disable
2026-06-15 15:31 UTC (2+ messages)
[PATCH v2 0/2] Unify fec enable/disable across the mst streams
2026-06-16 17:13 UTC (9+ messages)
` [PATCH v2 1/2] drm/i915/mst: Unify fec_enable across "
` [PATCH v2 2/2] drm/i915/display: Refcount for fec enable/disable
` ✓ i915.CI.Full: success for Unify fec enable/disable across the mst streams
[PULL] drm-intel-next-fixes
2026-06-17 10:05 UTC
[PATCH v2 0/2] Extend VRR safe window wait for VRR TG
2026-06-17 6:46 UTC (8+ messages)
` [PATCH v2 1/2] drm/i915/dsb: shift delayed-vblank DSL wait start by one scanline
` [PATCH v2 2/2] drm/i915/dsb: Use safe window path when VRR TG is used
` [PATCH v3 "
` ✓ i915.CI.BAT: success for Extend VRR safe window wait for VRR TG (rev3)
[PATCH RESEND v2] drm/i915/display: Program TRANS_VTOTAL from mode vtotal
2026-06-17 6:12 UTC (2+ messages)
` ✓ i915.CI.BAT: success for drm/i915/display: Program TRANS_VTOTAL from mode vtotal (rev4)
[PATCH v2 00/11] Enable CMRR in fixed-RR VRR path
2026-06-17 5:56 UTC (14+ messages)
` [PATCH v2 01/11] drm/i915/vrr: add per-CRTC vrr/cmrr debugfs control
` [PATCH v2 02/11] drm/i915/vrr: compute CMRR fractional timings generically
` [PATCH v2 03/11] drm/i915/vrr: dump CMRR state in the crtc state dump
` [PATCH v2 04/11] drm/i915/vrr: Move CMRR hw registers to fix refresh rate path
` [PATCH v2 05/11] drm/i915/vrr: Enable/Disable CMRR based on enable/disable preconditions
` [PATCH v2 06/11] drm/i915/display: Move CMRR crtc_state members under VRR
` [PATCH v2 07/11] drm/i915/vrr: Fix the CMRR enabling/disabling sequence
` [PATCH v2 08/11] drm/i915/vrr: Compare state and HW registers if platform supports CMRR
` [PATCH v2 09/11] drm/i915/vrr: Remove TODO as CMRR is exclusive to Adaptive mode
` [PATCH v2 10/11] drm/i915/vrr: Return from CMRR compute config in case of PSR2 enabled
` [PATCH v2 11/11] drm/i915/vrr: Enable cmrr
` ✓ i915.CI.BAT: success for Enable CMRR in fixed-RR VRR path (rev2)
` ✗ i915.CI.Full: failure "
[PATCH v1] drm/i915/display: Program TRANS_VTOTAL from mode vtotal
2026-06-17 5:32 UTC (5+ messages)
` ✗ i915.CI.BAT: failure for "
` ✓ i915.CI.BAT: success "
[PATCH] drm/i915/cx0: Remove unnecessary hdmi link rate function declaration
2026-06-17 5:13 UTC (3+ messages)
` ✓ i915.CI.BAT: success for "
[PATCH RESEND v2] drm/i915/display: Program TRANS_VTOTAL from mode vtotal
2026-06-17 4:58 UTC (2+ messages)
` ✗ Fi.CI.BUILD: failure for drm/i915/display: Program TRANS_VTOTAL from mode vtotal (rev3)
[PATCH v2] drm/i915/display: Program TRANS_VTOTAL from mode vtotal
2026-06-17 4:40 UTC
[PATCH v8 00/27] drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe
2026-06-17 1:32 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev16)
` ✗ i915.CI.Full: failure "
[PATCH] drm/i915/backlight: Set brightness to 0 on disable
2026-06-17 0:03 UTC (3+ messages)
` ✓ i915.CI.BAT: success for "
` ✗ i915.CI.Full: failure "
[PATCH v2 00/28] drm/i915/dp_link: Refactor DP link capability logic part1
2026-06-16 22:58 UTC (30+ messages)
` [PATCH v2 01/28] drm/i915/dp: Rename intel_dp_link_config to intel_dp_link_config_entry
` [PATCH v2 02/28] drm/i915/dp: Add struct intel_dp_link_config
` [PATCH v2 03/28] drm/i915/dp_link_caps: Introduce DP link capability module
` [PATCH v2 04/28] drm/i915/dp_link_caps: Move common rate helpers to link caps
` [PATCH v2 05/28] drm/i915/dp_link_caps: Move forced link param "
` [PATCH v2 06/28] drm/i915/dp: Simplify querying of forced link parameters
` [PATCH v2 07/28] drm/i915/dp_link_caps: Move forced and max link debugfs entries to link caps
` [PATCH v2 08/28] drm/i915/dp_link_training: Use helpers to get forced link params
` [PATCH v2 09/28] drm/i915/dp_link_caps: Move forced link params to link_caps
` [PATCH v2 10/28] drm/i915/dp_link_caps: Move link config helpers to link caps
` [PATCH v2 11/28] drm/i915/dp_link_caps: Move link config tracking to link_caps
` [PATCH v2 12/28] drm/i915/dp_link_caps: Rename helper updating the link configurations
` [PATCH v2 13/28] drm/i915/dp: Factor out helper to get link rate capabilities
` [PATCH v2 14/28] drm/i915/dp_link_caps: Pass supported link rates to link caps update
` [PATCH v2 15/28] drm/i915/dp_link_caps: Add helper to print all supported link rates
` [PATCH v2 16/28] drm/i915/dp_link_caps: Add helper to get the number of "
` [PATCH v2 17/28] drm/i915/dp_link_caps: Add helper to get common rate index
` [PATCH v2 18/28] drm/i915/dp_link_caps: Move tracking of common rates to link_caps struct
` [PATCH v2 19/28] drm/i915/dp_link_caps: Track max common lane count in link_caps
` [PATCH v2 20/28] drm/i915/dp_link_caps: Use max common lane count from link_caps
` [PATCH v2 21/28] drm/i915/dp_link_caps: Add helpers to get max link limits
` [PATCH v2 22/28] drm/i915/dp_link_caps: Add helpers to set "
` [PATCH v2 23/28] drm/i915/dp_link_caps: Add helper to reset "
` [PATCH v2 24/28] drm/i915/dp_link_caps: Add helper to reset link_caps state
` [PATCH v2 25/28] drm/i915/dp_link_caps: Move max link limits to link_caps
` [PATCH v2 26/28] drm/i915/dp_link_caps: Pass link_caps to static functions
` [PATCH v2 27/28] drm/i915/dp_link_caps: Pass link_caps to config update/lookup helpers
` [PATCH v2 28/28] drm/i915/dp_link_caps: Pass link_caps to common rate helpers
` ✓ i915.CI.BAT: success for drm/i915/dp_link: Refactor DP link capability logic part1
[PATCH v2] drm/i915/display: update to the BW buddy configuration
2026-06-16 21:48 UTC (3+ messages)
` ✓ i915.CI.BAT: success for drm/i915/display: update to the BW buddy configuration (rev2)
[PATCH v2] drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late
2026-06-16 20:16 UTC (4+ messages)
` ✓ i915.CI.BAT: success for drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late (rev2)
` ✗ i915.CI.Full: failure "
[PATCH] drm/i915/display: update to the BW buddy configuration
2026-06-16 18:43 UTC (4+ messages)
` ✗ i915.CI.BAT: failure for "
[CI v4 00/39] For CI only: DC3CO/CMTG validation series
2026-06-16 13:37 UTC (41+ messages)
` [CI v4 01/39] drm/i915/cmtg: Add intel_cmtg_is_allowed() for CMTG
` [CI v4 02/39] drm/i915/cmtg: Set CMTG clock select
` [CI v4 03/39] drm/i915/cmtg: Add CMTG transcoder offset in struct _device_info
` [CI v4 04/39] drm/i915/display: Pass target transcoder to intel_set_transcoder_timings()
` [CI v4 05/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder
` [CI v4 06/39] drm/i915/display: Skip DP_MIN_HBLANK_CTL programming for CMTG transcoders
` [CI v4 07/39] drm/i915/display: Pass transcoder to intel_set_transcoder_timings_lrr()
` [CI v4 08/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder in LRR path
` [CI v4 09/39] drm/i915/cmtg: Set timings for CMTG by using transcoder timing helpers
` [CI v4 10/39] drm/i915/vrr: Pass transcoder to intel_vrr_set_fixed_rr_timings()
` [CI v4 11/39] drm/i915/display: Rename cpu_transcoder parameter to transcoder in VRR fixed-rr path
` [CI v4 12/39] drm/i915/cmtg: Program VRR fixed-rate timings for CMTG transcoder
` [CI v4 13/39] drm/i915/cmtg: Program VRR control register "
` [CI v4 14/39] drm/i915/cmtg: Set link M/N "
` [CI v4 15/39] drm/i915/cmtg: Add hook to enable CMTG with sync to port
` [CI v4 16/39] drm/i915/cmtg: Add a hook to make eDP transcoder secondary
` [CI v4 17/39] drm/i915/cmtg: Modify existing hook to disable CMTG
` [CI v4 18/39] drm/i915/cmtg: Add CMTG HWGB programming
` [CI v4 19/39] drm/i915/cmtg: Add CMTG scan line programming
` [CI v4 20/39] drm/i915/cmtg: Add trigger to enable/disable cmtg
` [CI v4 21/39] drm/i915/cmtg: Restore CMTG after DC6 exit
` [CI v4 22/39] drm/i915/cmtg: Add CMTG interrupt handling
` [CI v4 23/39] drm/i915/display: Remove TGL DC3CO support
` [CI v4 24/39] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding
` [CI v4 25/39] drm/i915/display: Use FIELD_PREP() for DC state enable bits
` [CI v4 26/39] drm/i915/display: Add DC3CO DC_STATE enable/disable support
` [CI v4 27/39] drm/i915/display: Add HAS_DC3CO() macro
` [CI v4 28/39] drm/i915/display: Add DC3CO support check
` [CI v4 29/39] drm/i915/psr: Add psr2 deep sleep helper API
` [CI v4 30/39] drm/i915/display: Add DC3CO compute and set target state in commit tail
` [CI v4 31/39] drm/i915/display: Store DC3CO eligibility in PSR state
` [CI v4 32/39] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
` [CI v4 33/39] drm/i915/display: Enable DC3CO idle protocol in ALPM
` [CI v4 34/39] drm/i915/display: PSR Add delayed work to exit DC3CO
` [CI v4 35/39] drm/i915/display: Add helper to enable DC counter
` [CI v4 36/39] drm/i915/display: Add DC3CO count and residency in dmc debugfs
` [CI v4 37/39] drm/i915/display: Guard CMTG function calls
` [CI v4 38/39] drm/i915/display: Enable DC3CO DC state
` [CI v4 39/39] drm/i915/display: Mask RO bits in gen9_write_dc_state()
` ✗ Fi.CI.BUILD: failure for For CI only: DC3CO/CMTG validation series (rev5)
[PATCH v9 00/22] CMTG enablement
2026-06-16 12:56 UTC (16+ messages)
` [PATCH v9 08/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder in LRR path
` [PATCH v9 11/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder in VRR fixed-rr path
` [PATCH v9 17/22] drm/i915/cmtg: Modify existing hook to disable CMTG
` [PATCH v9 20/22] drm/i915/cmtg: Add trigger to enable/disable cmtg
` [PATCH v9 21/22] drm/i915/cmtg: Restore CMTG after DC6 exit
` [PATCH v9 22/22] drm/i915/cmtg: Add CMTG interrupt handling
` [PATCH v9 05/22] drm/i915/display: Rename cpu_transcoder parameter to transcoder
` ✓ i915.CI.Full: success for CMTG enablement (rev9)
[PATCH 0/4] drm/{i915,xe}: unify runtime pm calls
2026-06-16 10:09 UTC (3+ messages)
` [PATCH 4/4] drm/xe/display: unify runtime suspend/resume with i915 for non-d3cold
[PATCH v3 0/7] drm/i915/display: reduce the pm demand peak bw based on display data rate
2026-06-16 9:58 UTC (2+ messages)
` ✓ i915.CI.Full: success for drm/i915/display: reduce the pm demand peak bw based on display data rate (rev2)
Three monitors on HD4000
2026-06-16 9:49 UTC (2+ messages)
[PATCH] drm/intel: drop driver include from mchbar_regs.h
2026-06-16 9:44 UTC (3+ messages)
[PATCH 0/6] drm/i915/cdclk: CDCLK sanitization stuff
2026-06-16 8:26 UTC (13+ messages)
` [PATCH 1/6] drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a full PLL re-enable
` [PATCH 2/6] drm/i915/cdclk: Print the reason for the CDCLK sanitization
` [PATCH 3/6] drm/i915/cdclk Clean up CDCLK_CTL defines
` [PATCH 4/6] drm/i915/cdclk: Document CDCLK_CTL bits
` [PATCH 5/6] drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and use it
` [PATCH 6/6] drm/i915/cdclk: Use the TGL+ CD2x pipe select bits also on ICL
[PATCH] drm/i915/alpm: Move the check for PSR and Fixed RR in compute_config_late
2026-06-16 8:22 UTC (3+ messages)
[PATCH] drm/i915/drrs: Synchronize drrs activate with debugfs
2026-06-16 8:05 UTC (2+ messages)
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