From: "Sharma, Shashank" <shashank.sharma@intel.com>
To: Vidya Srinivas <vidya.srinivas@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function
Date: Wed, 14 Feb 2018 15:32:51 +0530 [thread overview]
Message-ID: <0519d428-c516-27da-3bb4-bfa3c80d65a3@intel.com> (raw)
In-Reply-To: <1518584256-25253-10-git-send-email-vidya.srinivas@intel.com>
Reviewed-by: Shashank Sharma <shashank.sharma@intel.com>
Regards
Shashank
On 2/14/2018 10:27 AM, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
>
> This patch splits skl_compute_wm/ddb functions into two parts.
> One adds all affected pipes after the commit to atomic_state structure
> and second part does compute the DDB.
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 157 ++++++++++++++++++++++------------------
> 1 file changed, 88 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d9f6563..ca3a783 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5058,69 +5058,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
> static int
> skl_compute_ddb(struct drm_atomic_state *state)
> {
> - struct drm_device *dev = state->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + const struct drm_i915_private *dev_priv = to_i915(state->dev);
> struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct intel_crtc *intel_crtc;
> struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
> - uint32_t realloc_pipes = pipes_modified(state);
> - int ret;
> -
> - /*
> - * If this is our first atomic update following hardware readout,
> - * we can't trust the DDB that the BIOS programmed for us. Let's
> - * pretend that all pipes switched active status so that we'll
> - * ensure a full DDB recompute.
> - */
> - if (dev_priv->wm.distrust_bios_wm) {
> - ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
> - state->acquire_ctx);
> - if (ret)
> - return ret;
> -
> - intel_state->active_pipe_changes = ~0;
> -
> - /*
> - * We usually only initialize intel_state->active_crtcs if we
> - * we're doing a modeset; make sure this field is always
> - * initialized during the sanitization process that happens
> - * on the first commit too.
> - */
> - if (!intel_state->modeset)
> - intel_state->active_crtcs = dev_priv->active_crtcs;
> - }
> -
> - /*
> - * If the modeset changes which CRTC's are active, we need to
> - * recompute the DDB allocation for *all* active pipes, even
> - * those that weren't otherwise being modified in any way by this
> - * atomic commit. Due to the shrinking of the per-pipe allocations
> - * when new active CRTC's are added, it's possible for a pipe that
> - * we were already using and aren't changing at all here to suddenly
> - * become invalid if its DDB needs exceeds its new allocation.
> - *
> - * Note that if we wind up doing a full DDB recompute, we can't let
> - * any other display updates race with this transaction, so we need
> - * to grab the lock on *all* CRTC's.
> - */
> - if (intel_state->active_pipe_changes) {
> - realloc_pipes = ~0;
> - intel_state->wm_results.dirty_pipes = ~0;
> - }
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *cstate;
> + int ret, i;
>
> - /*
> - * We're not recomputing for the pipes not included in the commit, so
> - * make sure we start with the current state.
> - */
> memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
>
> - for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
> - struct intel_crtc_state *cstate;
> -
> - cstate = intel_atomic_get_crtc_state(state, intel_crtc);
> - if (IS_ERR(cstate))
> - return PTR_ERR(cstate);
> -
> + for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
> ret = skl_allocate_pipe_ddb(cstate, ddb);
> if (ret)
> return ret;
> @@ -5182,23 +5129,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
> }
>
> static int
> -skl_compute_wm(struct drm_atomic_state *state)
> +skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
> {
> - struct drm_crtc *crtc;
> - struct drm_crtc_state *cstate;
> - struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> - struct skl_ddb_values *results = &intel_state->wm_results;
> struct drm_device *dev = state->dev;
> - struct skl_pipe_wm *pipe_wm;
> - bool changed = false;
> + const struct drm_i915_private *dev_priv = to_i915(dev);
> + const struct drm_crtc *crtc;
> + const struct drm_crtc_state *cstate;
> + struct intel_crtc *intel_crtc;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + uint32_t realloc_pipes = pipes_modified(state);
> int ret, i;
>
> /*
> * When we distrust bios wm we always need to recompute to set the
> * expected DDB allocations for each CRTC.
> */
> - if (to_i915(dev)->wm.distrust_bios_wm)
> - changed = true;
> + if (dev_priv->wm.distrust_bios_wm)
> + *changed = true;
>
> /*
> * If this transaction isn't actually touching any CRTC's, don't
> @@ -5209,14 +5156,86 @@ skl_compute_wm(struct drm_atomic_state *state)
> * hold _all_ CRTC state mutexes.
> */
> for_each_new_crtc_in_state(state, crtc, cstate, i)
> - changed = true;
> + *changed = true;
>
> - if (!changed)
> + if (!*changed)
> return 0;
>
> + /*
> + * If this is our first atomic update following hardware readout,
> + * we can't trust the DDB that the BIOS programmed for us. Let's
> + * pretend that all pipes switched active status so that we'll
> + * ensure a full DDB recompute.
> + */
> + if (dev_priv->wm.distrust_bios_wm) {
> + ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
> + state->acquire_ctx);
> + if (ret)
> + return ret;
> +
> + intel_state->active_pipe_changes = ~0;
> +
> + /*
> + * We usually only initialize intel_state->active_crtcs if we
> + * we're doing a modeset; make sure this field is always
> + * initialized during the sanitization process that happens
> + * on the first commit too.
> + */
> + if (!intel_state->modeset)
> + intel_state->active_crtcs = dev_priv->active_crtcs;
> + }
> +
> + /*
> + * If the modeset changes which CRTC's are active, we need to
> + * recompute the DDB allocation for *all* active pipes, even
> + * those that weren't otherwise being modified in any way by this
> + * atomic commit. Due to the shrinking of the per-pipe allocations
> + * when new active CRTC's are added, it's possible for a pipe that
> + * we were already using and aren't changing at all here to suddenly
> + * become invalid if its DDB needs exceeds its new allocation.
> + *
> + * Note that if we wind up doing a full DDB recompute, we can't let
> + * any other display updates race with this transaction, so we need
> + * to grab the lock on *all* CRTC's.
> + */
> + if (intel_state->active_pipe_changes) {
> + realloc_pipes = ~0;
> + intel_state->wm_results.dirty_pipes = ~0;
> + }
> +
> + /*
> + * We're not recomputing for the pipes not included in the commit, so
> + * make sure we start with the current state.
> + */
> + for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
> + struct intel_crtc_state *cstate;
> +
> + cstate = intel_atomic_get_crtc_state(state, intel_crtc);
> + if (IS_ERR(cstate))
> + return PTR_ERR(cstate);
> + }
> +
> + return 0;
> +}
> +
> +static int
> +skl_compute_wm(struct drm_atomic_state *state)
> +{
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> + struct skl_ddb_values *results = &intel_state->wm_results;
> + struct skl_pipe_wm *pipe_wm;
> + bool changed = false;
> + int ret, i;
> +
> /* Clear all dirty flags */
> results->dirty_pipes = 0;
>
> + ret = skl_ddb_add_affected_pipes(state, &changed);
> + if (ret || !changed)
> + return ret;
> +
> ret = skl_compute_ddb(state);
> if (ret)
> return ret;
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next prev parent reply other threads:[~2018-02-14 10:02 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-14 4:57 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-14 4:57 ` [PATCH 01/16] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-02-14 4:57 ` [PATCH 02/16] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
2018-02-14 4:57 ` [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-02-14 4:57 ` [PATCH 04/16] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
2018-02-14 9:36 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 05/16] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-02-14 9:41 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 06/16] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-02-14 4:57 ` [PATCH 07/16] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-02-14 4:57 ` [PATCH 08/16] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-02-14 9:47 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-14 10:02 ` Sharma, Shashank [this message]
2018-02-14 4:57 ` [PATCH 10/16] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-02-15 6:32 ` Sharma, Shashank
2018-02-15 9:28 ` Srinivas, Vidya
2018-02-14 4:57 ` [PATCH 11/16] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-02-15 6:34 ` Sharma, Shashank
2018-02-15 9:25 ` Srinivas, Vidya
2018-02-14 4:57 ` [PATCH 12/16] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-02-14 4:57 ` [PATCH 13/16] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-02-14 4:57 ` [PATCH 14/16] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-02-15 8:53 ` Sharma, Shashank
2018-02-15 9:18 ` Srinivas, Vidya
2018-02-14 4:57 ` [PATCH 15/16] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-02-15 9:22 ` Sharma, Shashank
2018-02-14 4:57 ` [PATCH 16/16] drm/i915: Enable YUV to RGB for Gen10 in Plane Ctrl Reg Vidya Srinivas
2018-02-15 11:03 ` Sharma, Shashank
2018-02-15 11:05 ` Sharma, Shashank
2018-02-14 5:24 ` [PATCH 00/16] Adding NV12 support Kristian Høgsberg
2018-02-14 8:32 ` Srinivas, Vidya
2018-02-14 5:46 ` ✗ Fi.CI.BAT: failure for Adding NV12 support (rev10) Patchwork
2018-02-14 12:33 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2018-02-14 12:37 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-02-14 13:07 ` Maarten Lankhorst
2018-02-14 14:03 ` Arkadiusz Hiler
2018-02-14 12:48 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 14:10 ` ✗ Fi.CI.CHECKPATCH: warning " Patchwork
2018-02-14 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-02-14 14:26 ` ✓ Fi.CI.BAT: success " Patchwork
2018-02-14 14:29 ` ✓ Fi.CI.IGT: " Patchwork
2018-02-14 14:48 ` Maarten Lankhorst
2018-02-14 18:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-02-14 20:02 ` ✗ Fi.CI.IGT: warning " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2018-02-21 10:20 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-21 10:20 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-15 2:39 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-15 2:39 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-13 9:51 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-13 9:52 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-06 13:02 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-06 13:02 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-02-06 12:58 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-02-06 12:58 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-01-22 12:03 [PATCH 00/16] Adding NV12 support Vidya Srinivas
2018-01-22 12:03 ` [PATCH 09/16] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
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