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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SA3PR11MB7556.namprd11.prod.outlook.com (2603:10b6:806:31f::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Wed, 5 Nov 2025 04:19:42 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9253.013; Wed, 5 Nov 2025 04:19:42 +0000 Message-ID: <08b53254-a364-4c5c-a472-d2f4cd3b25cb@intel.com> Date: Wed, 5 Nov 2025 09:49:36 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND, 03/22] drm/i915/vrr: Add VRR DC balance registers To: Mitul Golani , CC: , , References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-4-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251103053002.3002695-4-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > - Remove usage of dev_priv. (Jani, Nikula) > > --v3: > - Convert register address offset, from capital to small. (Ankit) > - Move mask bits near to register offsets. (Ankit) > > --v4: > - Use _MMIO_TRANS wherever possible. (Jani) > > --v5: > - Added LIVE Value registers for VMAX and FLIPLINE as provided by DMC fw > - For pipe B it is temporary and expected to change later once finalised. > > --v6: > - Add live value registers for DCB VMAX/FLIPLINE. > > --v7: > - Correct commit message file. (Jani Nikula) > - Add bits in highest to lowest order. (Jani Nikula) > > Signed-off-by: Mitul Golani > Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr_regs.h | 69 +++++++++++++++++++ > 1 file changed, 69 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > index ba9b9215dc11..f828db55d9b2 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h > @@ -8,6 +8,74 @@ > > #include "intel_display_reg_defs.h" > > +/* VRR registers */ > +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4 > +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4 > +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \ > + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B) > + > +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A 0x90700 > +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B 0x98700 > +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(trans) \ > + _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_A, \ > + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE_B) This is a bit awkward to read, can we have this in same line. I understand this will be more than 100 chars but IMO that should be alright. Regards, Ankit > +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) > +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) > +#define VRR_DCB_ADJ_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \ > + (flipline)) > + > +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8 > +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8 > +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \ > + _TRANS_VRR_DCB_ADJ_VMAX_CFG_B) > + > +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A 0x906F8 > +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B 0x986F8 > +#define TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_A, \ > + _TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE_B) > +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) > +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) > +#define VRR_DCB_ADJ_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax)) > + > +#define _TRANS_VRR_DCB_FLIPLINE_A 0x60418 > +#define _TRANS_VRR_DCB_FLIPLINE_B 0x61418 > +#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_FLIPLINE_A, \ > + _TRANS_VRR_DCB_FLIPLINE_B) > + > +#define _TRANS_VRR_DCB_FLIPLINE_LIVE_A 0x906FC > +#define _TRANS_VRR_DCB_FLIPLINE_LIVE_B 0x986FC > +#define TRANS_VRR_DCB_FLIPLINE_LIVE(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_FLIPLINE_LIVE_A, \ > + _TRANS_VRR_DCB_FLIPLINE_LIVE_B) > +#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0) > +#define VRR_DCB_FLIPLINE(flipline) REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \ > + (flipline)) > + > +#define _TRANS_VRR_DCB_VMAX_A 0x60414 > +#define _TRANS_VRR_DCB_VMAX_B 0x61414 > +#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_VMAX_A, \ > + _TRANS_VRR_DCB_VMAX_B) > +#define _TRANS_VRR_DCB_VMAX_LIVE_A 0x906F4 > +#define _TRANS_VRR_DCB_VMAX_LIVE_B 0x986F4 > +#define TRANS_VRR_DCB_VMAX_LIVE(trans) _MMIO_TRANS(trans, \ > + _TRANS_VRR_DCB_VMAX_LIVE_A, \ > + _TRANS_VRR_DCB_VMAX_LIVE_B) > +#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0) > +#define VRR_DCB_VMAX(vmax) REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax)) > + > +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0 > +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0 > +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \ > + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \ > + _TRANS_ADAPTIVE_SYNC_DCB_CTL_B) > +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) > + > #define _TRANS_VRR_CTL_A 0x60420 > #define _TRANS_VRR_CTL_B 0x61420 > #define _TRANS_VRR_CTL_C 0x62420 > @@ -19,6 +87,7 @@ > #define VRR_CTL_CMRR_ENABLE REG_BIT(27) > #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) > #define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) > +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) > #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) > #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) > #define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))