From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Round-up GTT allocations for unfenced surfaces to the next tile row Date: Sat, 26 Mar 2011 08:52:31 +0000 Message-ID: <0d30dc$ljoru2@orsmga001.jf.intel.com> References: <1301045779-8076-1-git-send-email-chris@chris-wilson.co.uk> <1301055385-4844-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 17DF19E75C for ; Sat, 26 Mar 2011 01:52:35 -0700 (PDT) In-Reply-To: <1301055385-4844-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Fri, 25 Mar 2011 12:16:25 +0000, Chris Wilson wrote: > We ensure that an allocated region within the GTT matches the proposed > usage restrictions. For fenced buffers on old hardware, this means > rounding up the allocation to the next power of two size and aligning it > to that size. For unfenced buffers, we need to ensure that the start and > end of the allocation is aligned to an even tile row. > > v2: Apply the allocation fixup to all devices I verified that it has no substantial impact on performance of gen4+ devices using cairo-gl/xlib. (Since cairo likes to exercise surface creation and reuse a lot.) However, I'm not sure if this truly prevents the corruption on i8xx with 2.14.0. Can somebody break out an old machine and test? -Chris -- Chris Wilson, Intel Open Source Technology Centre