From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH 1/5] drm/i915: Initialise g4x watermarks for
	disabled pipes
Date: Wed, 06 Apr 2011 07:59:37 +0100
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To: Keith Packard <keithp@keithp.com>, intel-gfx@lists.freedesktop.org
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On Tue, 05 Apr 2011 18:02:51 -0700, Keith Packard <keithp@keithp.com> wrote:
> On Tue, 05 Apr 2011 22:12:19 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> 
> > Indeed, I started by setting them to zero in the caller. Decided that
> > there was some precedent to use the guard_size as the minimum value for
> > unused planes (and so perhaps the unused planes on the unused pipes) and
> > so it was then natural to do it inside g4x_compute_wm. I guess it all
> > depends on how many FIFOs are split between the pipes. Using guard_size,
> > I believe, should be safest.
> 
> guard_size is probably better than random stack stuff. Any opinion on
> whether this should be done in g4x_update_wm instead of g4x_compute_wm0?

I'd prefer to keep the mucking around with intel_watermak_params in the
one spot. How about:

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f1798f2..dbe11eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3799,11 +3799,14 @@ static bool g4x_compute_wm0(struct drm_device *dev,
 	int line_time_us, line_count;
 	int entries, tlb_miss;
 
+	/* The FIFO requires a minimum number of entries (the guard size)
+	 * as it switches between planes:
+	 */
+	*cursor_wm = cursor->guard_size;
+	*plane_wm = display->guard_size;
+
 	crtc = intel_get_crtc_for_plane(dev, plane);
-	if (crtc->fb == NULL || !crtc->enabled) {
-		*cursor_wm = *plane_wm = display->guard_size;
+	if (crtc->fb == NULL || !crtc->enabled)
 		return false;
-	}
 
 	htotal = crtc->mode.htotal;
 	hdisplay = crtc->mode.hdisplay;
@@ -3816,7 +3819,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
 	if (tlb_miss > 0)
 		entries += tlb_miss;
 	entries = DIV_ROUND_UP(entries, display->cacheline_size);
-	*plane_wm = entries + display->guard_size;
+	*plane_wm += entries;
 	if (*plane_wm > (int)display->max_wm)
 		*plane_wm = display->max_wm;
 
@@ -3828,7 +3831,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
 	if (tlb_miss > 0)
 		entries += tlb_miss;
 	entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
-	*cursor_wm = entries + cursor->guard_size;
+	*cursor_wm += entries;
 	if (*cursor_wm > (int)cursor->max_wm)
 		*cursor_wm = (int)cursor->max_wm;
 

-- 
Chris Wilson, Intel Open Source Technology Centre