From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Prevent use of pages >4GiB on 965G[M] Date: Thu, 21 Apr 2011 07:03:13 +0100 Message-ID: <0d30dc$lu8ama@orsmga001.jf.intel.com> References: <1303058252-16961-1-git-send-email-chris@chris-wilson.co.uk> <87oc40o3o0.fsf@pollan.anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 7D99D9E94F for ; Wed, 20 Apr 2011 23:03:17 -0700 (PDT) In-Reply-To: <87oc40o3o0.fsf@pollan.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eric Anholt , intel-gfx@lists.freedesktop.org Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 20 Apr 2011 17:21:03 -0700, Eric Anholt wrote: > On Sun, 17 Apr 2011 17:37:32 +0100, Chris Wilson wrote: > > The 965G (Broadwater) and 965GM (Crestline) chipsets had many errata in > > handling pages allocation above 4GiB. So we should be careful never to > > allocate and attempt to pass such through to the GPU and so limit > > ourselves to GFP_DMA32 on those chipsets. > > Unfortunate to see this -- were there more particular bugs in >4GB > handling found, or is it just "I'm tired of worrying about it, let's > avoid this class of problem"? I'm not saying "no" to this patch for > either answer, just curious. It's an investigatory patch because 965GM is still misbehaving, and those warnings in the docs scared me. A solution in search of a problem, i.e. it may help someone and that would be very useful to know. -Chris -- Chris Wilson, Intel Open Source Technology Centre