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12 Jul 2023 07:24:34 -0700 Message-ID: <0fd1ecad-c8ae-0dde-6d97-12a66cc7936b@linux.intel.com> Date: Wed, 12 Jul 2023 16:24:31 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Content-Language: en-US To: Andi Shyti , Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala References: <20230627094327.134775-1-andi.shyti@linux.intel.com> <20230627094327.134775-4-andi.shyti@linux.intel.com> From: Nirmoy Das In-Reply-To: <20230627094327.134775-4-andi.shyti@linux.intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/gt: Poll aux invalidation register bit on invalidation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel GFX Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On 6/27/2023 11:43 AM, Andi Shyti wrote: > From: Jonathan Cavitt > > For platforms that use Aux CCS, wait for aux invalidation to > complete by checking the aux invalidation register bit is > cleared. > > Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") > Signed-off-by: Jonathan Cavitt > Signed-off-by: Andi Shyti > Cc: Mika Kuoppala > Cc: # v5.8+ Reviewed-by: Nirmoy Das > --- > drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 17 +++++++++++++---- > drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + > 2 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > index e10e1ad0e841f..83cddd9cb8b56 100644 > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > @@ -174,6 +174,16 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv > *cs++ = AUX_INV; > *cs++ = MI_NOOP; > > + *cs++ = MI_SEMAPHORE_WAIT_TOKEN | > + MI_SEMAPHORE_REGISTER_POLL | > + MI_SEMAPHORE_POLL | > + MI_SEMAPHORE_SAD_EQ_SDD; > + *cs++ = 0; > + *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; > + *cs++ = 0; > + *cs++ = 0; > + *cs++ = MI_NOOP; > + > return cs; > } > > @@ -274,10 +284,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > else if (engine->class == COMPUTE_CLASS) > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > + count = 8; > if (!HAS_FLAT_CCS(rq->engine->i915)) > - count = 8 + 4; > - else > - count = 8; > + count += 10; > > cs = intel_ring_begin(rq, count); > if (IS_ERR(cs)) > @@ -320,7 +329,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) > aux_inv = rq->engine->mask & > ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); > if (aux_inv) > - cmd += 4; > + cmd += 10; > } > } > > diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > index 5d143e2a8db03..02125a1db2796 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h > @@ -121,6 +121,7 @@ > #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) > #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ > #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */ > +#define MI_SEMAPHORE_REGISTER_POLL (1 << 16) > #define MI_SEMAPHORE_POLL (1 << 15) > #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12) > #define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12)