From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D391ECCFA13 for ; Wed, 29 Apr 2026 10:26:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3AEBD10EF72; Wed, 29 Apr 2026 10:26:00 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="e0JS+H0c"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3BA1510EF70; Wed, 29 Apr 2026 10:25:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777458359; x=1808994359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RJIeOUReL1HPlYaEa1QrK/WwbIo4fI32BqN+eDn08ZI=; b=e0JS+H0cyz/JEtfo+VHtfFhdOHCCWUE30TXH/PSYQ0l1DqY8Zi5Tumph 5/zJW0KLWGKATA2rnuvZoWl96uPV4n9BTnZqajkoKP/kgj/fbATFcnHlC 7H+whpn96XWgtG9fIoxoH+m/ID5/w7cjp7UR0nQmOmlyqTfvZG/7iQgvT xSEvLyxe2BkumwfStyiZvX+c8YPNIdY8CKNfEER0kvliyEwQjxHs116LH S0uzpfVTo1ihd2q5E3o2AbOx80VILzNBW/gf+7cXZEArC8TUGh6VOGAhU MG6ZhqdWYGDZHV56Vtt/DXSaZSbJbq1qClcwMJYLndwoEsM2jvsgRxaez g==; X-CSE-ConnectionGUID: GJP85EMaSDqkScUM9y3OTw== X-CSE-MsgGUID: OpsYVUYxSj6So/OjqlxIzA== X-IronPort-AV: E=McAfee;i="6800,10657,11770"; a="103838213" X-IronPort-AV: E=Sophos;i="6.23,205,1770624000"; d="scan'208";a="103838213" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 03:25:59 -0700 X-CSE-ConnectionGUID: d3PXnul7RaOcOw8r93Tdxw== X-CSE-MsgGUID: psZnC9DwSPSY4GbD60XN2g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,205,1770624000"; d="scan'208";a="257784391" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.245.175]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2026 03:25:54 -0700 From: Jani Nikula To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH 13/15] drm/i915/irq: add intel_display_irq_postinstall() to irq funcs Date: Wed, 29 Apr 2026 13:24:53 +0300 Message-ID: <113f97dd588404acbe03ff9bbffbcfde054addd1.1777458161.git.jani.nikula@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland Content-Transfer-Encoding: 8bit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Call the platform specific display irq postinstall hooks via intel_display_irq_postinstall(). Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_irq.c | 24 ++++++++++++++----- .../gpu/drm/i915/display/intel_display_irq.h | 7 +----- drivers/gpu/drm/i915/i915_irq.c | 16 ++++++------- drivers/gpu/drm/xe/display/xe_display.c | 2 +- 4 files changed, 28 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 7505652257d8..6ba094a0df66 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1981,7 +1981,7 @@ u32 i9xx_display_irq_enable_mask(struct intel_display *display) return enable_mask; } -void i915_display_irq_postinstall(struct intel_display *display) +static void i915_display_irq_postinstall(struct intel_display *display) { /* * Interrupt setup is already guaranteed to be single-threaded, this is @@ -1995,7 +1995,7 @@ void i915_display_irq_postinstall(struct intel_display *display) i915_enable_asle_pipestat(display); } -void i965_display_irq_postinstall(struct intel_display *display) +static void i965_display_irq_postinstall(struct intel_display *display) { /* * Interrupt setup is already guaranteed to be single-threaded, this is @@ -2057,7 +2057,7 @@ static void _vlv_display_irq_postinstall(struct intel_display *display) irq_init(display, VLV_IRQ_REGS, display->irq.vlv_imr_mask, enable_mask); } -void vlv_display_irq_postinstall(struct intel_display *display) +static void vlv_display_irq_postinstall(struct intel_display *display) { spin_lock_irq(&display->irq.lock); if (display->irq.vlv_display_irqs_enabled) @@ -2268,7 +2268,7 @@ void valleyview_disable_display_irqs(struct intel_display *display) spin_unlock_irq(&display->irq.lock); } -void ilk_de_irq_postinstall(struct intel_display *display) +static void ilk_de_irq_postinstall(struct intel_display *display) { u32 display_mask, extra_mask; @@ -2312,7 +2312,7 @@ void ilk_de_irq_postinstall(struct intel_display *display) static void mtp_irq_postinstall(struct intel_display *display); static void icp_irq_postinstall(struct intel_display *display); -void gen8_de_irq_postinstall(struct intel_display *display) +static void gen8_de_irq_postinstall(struct intel_display *display) { u32 de_pipe_masked = gen8_de_pipe_fault_mask(display) | GEN8_PIPE_CDCLK_CRC_DONE; @@ -2439,7 +2439,7 @@ static void icp_irq_postinstall(struct intel_display *display) irq_init(display, SDE_IRQ_REGS, ~mask, 0xffffffff); } -void gen11_de_irq_postinstall(struct intel_display *display) +static void gen11_de_irq_postinstall(struct intel_display *display) { if (!HAS_DISPLAY(display)) return; @@ -2451,30 +2451,37 @@ void gen11_de_irq_postinstall(struct intel_display *display) struct intel_display_irq_funcs { void (*reset)(struct intel_display *display); + void (*postinstall)(struct intel_display *display); }; struct intel_display_irq_funcs gen11_display_irq_funcs = { .reset = gen11_display_irq_reset, + .postinstall = gen11_de_irq_postinstall, }; struct intel_display_irq_funcs gen8_display_irq_funcs = { .reset = gen8_display_irq_reset, + .postinstall = gen8_de_irq_postinstall, }; struct intel_display_irq_funcs vlv_display_irq_funcs = { .reset = vlv_display_irq_reset, + .postinstall = vlv_display_irq_postinstall, }; struct intel_display_irq_funcs ilk_display_irq_funcs = { .reset = ilk_display_irq_reset, + .postinstall = ilk_de_irq_postinstall, }; struct intel_display_irq_funcs i965_display_irq_funcs = { .reset = i9xx_display_irq_reset, + .postinstall = i965_display_irq_postinstall, }; struct intel_display_irq_funcs i915_display_irq_funcs = { .reset = i9xx_display_irq_reset, + .postinstall = i915_display_irq_postinstall, }; void intel_display_irq_reset(struct intel_display *display) @@ -2482,6 +2489,11 @@ void intel_display_irq_reset(struct intel_display *display) display->irq.funcs->reset(display); } +void intel_display_irq_postinstall(struct intel_display *display) +{ + display->irq.funcs->postinstall(display); +} + void intel_display_irq_init(struct intel_display *display) { spin_lock_init(&display->irq.lock); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h b/drivers/gpu/drm/i915/display/intel_display_irq.h index 21b2145656cd..fd9873ce9755 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.h +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h @@ -59,14 +59,9 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); void intel_display_irq_reset(struct intel_display *display); +void intel_display_irq_postinstall(struct intel_display *display); u32 i9xx_display_irq_enable_mask(struct intel_display *display); -void i915_display_irq_postinstall(struct intel_display *display); -void i965_display_irq_postinstall(struct intel_display *display); -void vlv_display_irq_postinstall(struct intel_display *display); -void ilk_de_irq_postinstall(struct intel_display *display); -void gen8_de_irq_postinstall(struct intel_display *display); -void gen11_de_irq_postinstall(struct intel_display *display); u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7e0ec9294d70..7ffa0e8c5608 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -724,7 +724,7 @@ static void ilk_irq_postinstall(struct drm_i915_private *dev_priv) gen5_gt_irq_postinstall(to_gt(dev_priv)); - ilk_de_irq_postinstall(display); + intel_display_irq_postinstall(display); } static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) @@ -733,7 +733,7 @@ static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv) gen5_gt_irq_postinstall(to_gt(dev_priv)); - vlv_display_irq_postinstall(display); + intel_display_irq_postinstall(display); intel_uncore_write(&dev_priv->uncore, VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER); @@ -744,7 +744,7 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv) struct intel_display *display = dev_priv->display; gen8_gt_irq_postinstall(to_gt(dev_priv)); - gen8_de_irq_postinstall(display); + intel_display_irq_postinstall(display); gen8_master_intr_enable(intel_uncore_regs(&dev_priv->uncore)); } @@ -757,7 +757,7 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) u32 gu_misc_masked = GEN11_GU_MISC_GSE; gen11_gt_irq_postinstall(gt); - gen11_de_irq_postinstall(display); + intel_display_irq_postinstall(display); gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); @@ -778,7 +778,7 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) gen2_irq_init(uncore, GEN11_GU_MISC_IRQ_REGS, ~gu_misc_masked, gu_misc_masked); - gen11_de_irq_postinstall(display); + intel_display_irq_postinstall(display); dg1_master_intr_enable(intel_uncore_regs(uncore)); intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); @@ -790,7 +790,7 @@ static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) gen8_gt_irq_postinstall(to_gt(dev_priv)); - vlv_display_irq_postinstall(display); + intel_display_irq_postinstall(display); intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); @@ -888,7 +888,7 @@ static void i915_irq_postinstall(struct drm_i915_private *dev_priv) gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); - i915_display_irq_postinstall(display); + intel_display_irq_postinstall(display); } static irqreturn_t i915_irq_handler(int irq, void *arg) @@ -997,7 +997,7 @@ static void i965_irq_postinstall(struct drm_i915_private *dev_priv) gen2_irq_init(uncore, GEN2_IRQ_REGS, dev_priv->gen2_imr_mask, enable_mask); - i965_display_irq_postinstall(display); + intel_display_irq_postinstall(display); } static irqreturn_t i965_irq_handler(int irq, void *arg) diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index d6a4546fbe94..736a5e6938d6 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -245,7 +245,7 @@ void xe_display_irq_postinstall(struct xe_device *xe) if (!xe->info.probe_display) return; - gen11_de_irq_postinstall(display); + intel_display_irq_postinstall(display); } static bool suspend_to_idle(void) -- 2.47.3