From mboxrd@z Thu Jan  1 00:00:00 1970
From: Peter Clifton <pcjc2@cam.ac.uk>
Subject: Speed boost disabling RCC clock gating ECO
Date: Sat, 30 Oct 2010 03:34:37 +0100
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Hi guys,

Just a note on a data-point I found here:

sudo intel_reg_read 0x21D0
[sudo] password for pcjc2: 
0x21D0 : 0x307

sudo intel_reg_write 0x21D0 0x1000207
Value before: 0x307
Value after: 0x207


This boosted FPS of my displaylist frame benchmark from 35fps to 37fps.

This was clearing bit 8 of ECOSKPD, which is controlling the following
ECO:

Clock gating for the RCC (Disable one clock gate cell)


Any chance someone knows why the ECO is in place, or whether it is
dangerous to disable?

I also noticed that the specs for bit 12 and 9 (working around a CLIP
bug) are set in an invalid state according to the G45 PRM.

I have bit 12=0, bit9=1

This does match the expected default setting though.. is there a typo in
the PRM (Vol1a, P.322.) mixing bits 9 and 12 around in the table?


-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)