From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Clifton Subject: PATCH: Fixup comment about alignment for BLT in Mesa Date: Tue, 09 Nov 2010 22:00:36 +0000 Message-ID: <1289340036.9101.0.camel@pcjc2lap> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=-TbDH9cfhtMmTNsvmkpwJ" Return-path: Received: from ppsw-51.csi.cam.ac.uk (ppsw-51.csi.cam.ac.uk [131.111.8.151]) by gabe.freedesktop.org (Postfix) with ESMTP id 59A889E811 for ; Tue, 9 Nov 2010 14:00:39 -0800 (PST) Received: from client-86-31-82-85.midd.adsl.virginmedia.com ([86.31.82.85]:22803 helo=[192.168.1.2]) by ppsw-51.csi.cam.ac.uk (smtp.hermes.cam.ac.uk [131.111.8.158]:465) with esmtpsa (LOGIN:pcjc2) (SSLv3:DHE-RSA-CAMELLIA256-SHA:256) id 1PFwF4-0007so-WP (Exim 4.72) for intel-gfx@lists.freedesktop.org (return-path ); Tue, 09 Nov 2010 22:00:38 +0000 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Mailing list List-Id: intel-gfx@lists.freedesktop.org --=-TbDH9cfhtMmTNsvmkpwJ Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit -- Peter Clifton Electrical Engineering Division, Engineering Department, University of Cambridge, 9, JJ Thomson Avenue, Cambridge CB3 0FA Tel: +44 (0)7729 980173 - (No signal in the lab!) Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me) --=-TbDH9cfhtMmTNsvmkpwJ Content-Disposition: attachment; filename="0001-drm-intel-Add-assert-check-for-blitting-alignment.patch" Content-Type: text/x-patch; name="0001-drm-intel-Add-assert-check-for-blitting-alignment.patch"; charset="UTF-8" Content-Transfer-Encoding: 7bit >>From 18072c138b7cca626f8b45dfae2c6cb29a91aaf8 Mon Sep 17 00:00:00 2001 From: Peter Clifton Date: Tue, 9 Nov 2010 21:45:23 +0000 Subject: [PATCH] drm/intel: Add assert check for blitting alignment. Also fixup code comment to reflect that the GPU requires DWORD alignment, but in this case does not actually pass the value "in DWORDs" as I previously stated. --- src/mesa/drivers/dri/intel/intel_blit.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index 7118898..c2917e9 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -483,8 +483,8 @@ intel_emit_linear_blit(struct intel_context *intel, /* Blits are in a different ringbuffer so we don't use them. */ assert(intel->gen < 6); - /* The pitch hits the GPU as a is a signed value, IN DWORDs. - * But we want width to match pitch. Max width is (1 << 15 - 1), + /* The pitch given to the GPU must be DWORD aligned, and + * we want width to match pitch. Max width is (1 << 15 - 1), * rounding that down to the nearest DWORD is 1 << 15 - 4 */ pitch = MIN2(size, (1 << 15) - 4); @@ -502,6 +502,7 @@ intel_emit_linear_blit(struct intel_context *intel, dst_offset += pitch * height; size -= pitch * height; assert (size < (1 << 15)); + assert ((size & 3) == 0); /* Pitch must be DWORD aligned */ if (size != 0) { ok = intelEmitCopyBlit(intel, 1, size, src_bo, src_offset, I915_TILING_NONE, -- 1.7.1 --=-TbDH9cfhtMmTNsvmkpwJ Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --=-TbDH9cfhtMmTNsvmkpwJ--