From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Wang Subject: [PATCH] drm/i915: Add cached bo create interface Date: Tue, 14 Dec 2010 12:56:00 +0800 Message-ID: <1292302562-5800-2-git-send-email-zhenyuw@linux.intel.com> References: <1292302562-5800-1-git-send-email-zhenyuw@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id BBF969E738 for ; Mon, 13 Dec 2010 20:56:20 -0800 (PST) In-Reply-To: <1292302562-5800-1-git-send-email-zhenyuw@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Some BO is required to have cached attribute in GTT, e.g PIPE_CONTROL store DW buffer used for occlusion query function. This one adds new flags for that within bo create ioctl. Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_dma.c | 3 +++ drivers/gpu/drm/i915/i915_gem.c | 4 ++++ include/drm/i915_drm.h | 5 ++++- 3 files changed, 11 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index e9fb895..df5a248 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -778,6 +778,9 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_COHERENT_RINGS: value = 1; break; + case I915_PARAM_HAS_CREATE_CACHED: + value = 1; + break; default: DRM_DEBUG_DRIVER("Unknown parameter %d\n", param->param); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 27fa2a1..8bc5d05 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -216,6 +216,10 @@ i915_gem_create_ioctl(struct drm_device *dev, void *data, return ret; } + /* Setup required CPU cached bit for bo, e.g query obj */ + if (args->flags == DRM_I915_GEM_CREATE_CACHED) + obj->agp_type = AGP_USER_CACHED_MEMORY; + /* drop reference from allocate - handle holds it now */ drm_gem_object_unreference(&obj->base); trace_i915_gem_object_create(obj); diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index a2776e2..b34db99 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -289,6 +289,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_BLT 11 #define I915_PARAM_HAS_RELAXED_FENCING 12 #define I915_PARAM_HAS_COHERENT_RINGS 13 +#define I915_PARAM_HAS_CREATE_CACHED 14 typedef struct drm_i915_getparam { int param; @@ -370,6 +371,8 @@ struct drm_i915_gem_init { __u64 gtt_end; }; +#define DRM_I915_GEM_CREATE_CACHED 1 + struct drm_i915_gem_create { /** * Requested size for the object. @@ -383,7 +386,7 @@ struct drm_i915_gem_create { * Object handles are nonzero. */ __u32 handle; - __u32 pad; + __u32 flags; }; struct drm_i915_gem_pread { -- 1.7.1