From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Fisher Subject: [regression] drm/i915: Flush pending writes on i830/i845 after updating GTT Date: Thu, 30 Dec 2010 10:36:35 +0100 Message-ID: <1293701795.5595.7.camel@zwerg> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.gmx.net (mailout-de.gmx.net [213.165.64.23]) by gabe.freedesktop.org (Postfix) with SMTP id 67C9A9EB49 for ; Thu, 30 Dec 2010 01:36:38 -0800 (PST) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Hi, after this patch i get some rendering issues on my Intel DG45ID board, (Vendor: 0x8086, Device: 0x2e22, Revision: 0x03 (A3)) removing this lines fix it: diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index cecaa07..3a12cbf 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2148,8 +2148,8 @@ i915_gem_flush_ring(struct drm_device *dev, uint32_t invalidate_domains, uint32_t flush_domains) { - if (list_empty(&ring->gpu_write_list)) - return; +// if (list_empty(&ring->gpu_write_list)) +// return; ring->flush(ring, invalidate_domains, flush_domains); i915_gem_process_flushing_list(dev, flush_domains, ring); commit 15056d2c06862627ead868e035fcacc59dce1b1a Author: Chris Wilson Date: Tue Dec 21 17:04:23 2010 +0000 drm/i915: Flush pending writes on i830/i845 after updating GTT There is an erratum on these two chipsets that causes the wrong PTE entries to be invalidate after updating the GTT and when used from the BLT engine. The workaround is to flush any pending writes before those PTEs are used by the BLT. Signed-off-by: Chris Wilson -- Regards, Alexey