From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexey Fisher Subject: Re: [PATCH] drm/i915: Make the ring IMR handling private Date: Wed, 05 Jan 2011 12:54:23 +0100 Message-ID: <1294228463.5957.1.camel@zwerg> References: <1294221764.5749.6.camel@zwerg> <1294223808-9712-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.gmx.net (mailout-de.gmx.net [213.165.64.22]) by gabe.freedesktop.org (Postfix) with SMTP id 4D4AC9E747 for ; Wed, 5 Jan 2011 03:54:27 -0800 (PST) In-Reply-To: <1294223808-9712-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Tested. It's working. Thank you. Am Mittwoch, den 05.01.2011, 10:36 +0000 schrieb Chris Wilson: > As the IMR for the USER interrupts are not modified elsewhere, we can > separate the spinlock used for these from that of hpd and pipestats. > Those two IMR are manipulated under an IRQ and so need heavier locking. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 26 ++++++++++++++------------ > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 2 files changed, 15 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 13cad98..03e3370 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -526,7 +526,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring) > if (!dev->irq_enabled) > return false; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (ring->irq_refcount++ == 0) { > if (HAS_PCH_SPLIT(dev)) > ironlake_enable_irq(dev_priv, > @@ -534,7 +534,7 @@ render_ring_get_irq(struct intel_ring_buffer *ring) > else > i915_enable_irq(dev_priv, I915_USER_INTERRUPT); > } > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > > return true; > } > @@ -545,7 +545,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring) > struct drm_device *dev = ring->dev; > drm_i915_private_t *dev_priv = dev->dev_private; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (--ring->irq_refcount == 0) { > if (HAS_PCH_SPLIT(dev)) > ironlake_disable_irq(dev_priv, > @@ -554,7 +554,7 @@ render_ring_put_irq(struct intel_ring_buffer *ring) > else > i915_disable_irq(dev_priv, I915_USER_INTERRUPT); > } > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > } > > void intel_ring_setup_status_page(struct intel_ring_buffer *ring) > @@ -620,10 +620,10 @@ ring_get_irq(struct intel_ring_buffer *ring, u32 flag) > if (!dev->irq_enabled) > return false; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (ring->irq_refcount++ == 0) > ironlake_enable_irq(dev_priv, flag); > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > > return true; > } > @@ -634,10 +634,10 @@ ring_put_irq(struct intel_ring_buffer *ring, u32 flag) > struct drm_device *dev = ring->dev; > drm_i915_private_t *dev_priv = dev->dev_private; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (--ring->irq_refcount == 0) > ironlake_disable_irq(dev_priv, flag); > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > } > > static bool > @@ -649,13 +649,13 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) > if (!dev->irq_enabled) > return false; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (ring->irq_refcount++ == 0) { > ring->irq_mask &= ~rflag; > I915_WRITE_IMR(ring, ring->irq_mask); > ironlake_enable_irq(dev_priv, gflag); > } > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > > return true; > } > @@ -666,13 +666,13 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) > struct drm_device *dev = ring->dev; > drm_i915_private_t *dev_priv = dev->dev_private; > > - spin_lock(&dev_priv->irq_lock); > + spin_lock(&ring->irq_lock); > if (--ring->irq_refcount == 0) { > ring->irq_mask |= rflag; > I915_WRITE_IMR(ring, ring->irq_mask); > ironlake_disable_irq(dev_priv, gflag); > } > - spin_unlock(&dev_priv->irq_lock); > + spin_unlock(&ring->irq_lock); > } > > static bool > @@ -814,6 +814,8 @@ int intel_init_ring_buffer(struct drm_device *dev, > INIT_LIST_HEAD(&ring->active_list); > INIT_LIST_HEAD(&ring->request_list); > INIT_LIST_HEAD(&ring->gpu_write_list); > + > + spin_lock_init(&ring->irq_lock); > ring->irq_mask = ~0; > > if (I915_NEED_GFX_HWS(dev)) { > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 6b1d9a5..be9087e 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -55,6 +55,7 @@ struct intel_ring_buffer { > int effective_size; > struct intel_hw_status_page status_page; > > + spinlock_t irq_lock; > u32 irq_refcount; > u32 irq_mask; > u32 irq_seqno; /* last seq seem at irq time */ -- Regards, Alexey