From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eric Anholt Subject: WIP POSTING_READ fix series Date: Fri, 3 Jun 2011 12:20:18 -0700 Message-ID: <1307128822-9709-1-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from annarchy.freedesktop.org (annarchy.freedesktop.org [131.252.210.176]) by gabe.freedesktop.org (Postfix) with ESMTP id C244B9E762 for ; Fri, 3 Jun 2011 12:20:26 -0700 (PDT) Received: from pollan.anholt.net (annarchy.freedesktop.org [127.0.0.1]) by annarchy.freedesktop.org (Postfix) with ESMTP id 2F34C13004E for ; Fri, 3 Jun 2011 12:20:26 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Here's what I've been talking about on IRC today. Patch 3 appears to make things work. Patch 4 should work, but re-breaks things (hangs but no dmesg complaints). I want to understand why, but I'm running out of theories. Perhaps there's some period of time where a write has been PCI write posted but has not yet appeared in the GT FIFO? Or perhaps there's some time after GT FIFO but before it's really handled by hardware? Note that I was also able to fix the problem without this series by just POSTING_READing 4 times instead of 1.