From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adam Jackson Subject: [PATCH 2/2] drm/i915: Don't do MTRR setup if PAT is enabled Date: Wed, 14 Mar 2012 11:22:11 -0400 Message-ID: <1331738531-10181-2-git-send-email-ajax@redhat.com> References: <1331738531-10181-1-git-send-email-ajax@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTP id 988A39E80F for ; Wed, 14 Mar 2012 08:22:13 -0700 (PDT) Received: from int-mx01.intmail.prod.int.phx2.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q2EFMDRC016478 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 14 Mar 2012 11:22:13 -0400 Received: from ihatethathostname.lab.bos.redhat.com (ihatethathostname.lab.bos.redhat.com [10.16.43.238]) by int-mx01.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id q2EFMCgi018518 for ; Wed, 14 Mar 2012 11:22:12 -0400 In-Reply-To: <1331738531-10181-1-git-send-email-ajax@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Some newer BIOSes are shipping with all MTRRs already populated. These BIOSes are all on machines with sufficiently new CPUs that the referenced errata doesn't apply anyway, so just don't try to claim the MTRR. Signed-off-by: Adam Jackson --- drivers/gpu/drm/i915/i915_dma.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index d52f4a5..cb648d8 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -43,6 +43,7 @@ #include #include #include +#include static void i915_write_hws_pga(struct drm_device *dev) { @@ -1897,6 +1898,11 @@ static void i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, unsigned long size) { +#if defined(CONFIG_X86_PAT) + if (cpu_has_pat) + return; +#endif + /* Set up a WC MTRR for non-PAT systems. This is more common than * one would think, because the kernel disables PAT on first * generation Core chips because WC PAT gets overridden by a UC -- 1.7.7.6