From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: [PATCH 13/37] drm/i915: add support for SBI ops Date: Wed, 21 Mar 2012 22:09:48 -0300 Message-ID: <1332378612-3814-14-git-send-email-eugeni.dodonov@intel.com> References: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id CE0F7A0D12 for ; Wed, 21 Mar 2012 18:30:54 -0700 (PDT) In-Reply-To: <1332378612-3814-1-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org With Lynx Point, we need to use SBI to communicate with the display clock control. This commit adds helper functions to access the registers via SBI. Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index de1ba19..c225de4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1198,6 +1198,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) POSTING_READ(reg); } +/* SBI access */ +static inline void +SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value) +{ + if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to become ready\n"); + + I915_WRITE(SBI_ADDR, + (reg << 16)); + I915_WRITE(SBI_DATA, + value); + I915_WRITE(SBI_CTL_STAT, + SBI_READY | + SBI_CTL_OP_CRWR); + + if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); +} + +static inline u32 +SBI_READ(struct drm_i915_private *dev_priv, u16 reg) +{ + u32 value; + if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to become ready\n"); + + I915_WRITE(SBI_ADDR, + (reg << 16)); + I915_WRITE(SBI_CTL_STAT, + SBI_READY | + SBI_CTL_OP_CRRD); + + if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0, + 10)) + DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); + + value = I915_READ(SBI_DATA); + + return value; +} + /** * intel_enable_pch_pll - enable PCH PLL * @dev_priv: i915 private structure -- 1.7.9.2