From: Eugeni Dodonov <eugeni.dodonov@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Eugeni Dodonov <eugeni.dodonov@intel.com>
Subject: [PATCH 05/41] drm/i915: add support for power wells
Date: Thu, 29 Mar 2012 12:32:21 -0300 [thread overview]
Message-ID: <1333035177-19607-6-git-send-email-eugeni.dodonov@intel.com> (raw)
In-Reply-To: <1333035177-19607-1-git-send-email-eugeni.dodonov@intel.com>
This defines the registers used by different power wells.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..b13ed38 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3850,4 +3850,17 @@
#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf << 16)
#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
+/* HSW Power Wells */
+#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
+#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
+#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
+#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
+#define HSW_PWR_WELL_ENABLE (1<<31)
+#define HSW_PWR_WELL_STATE (1<<30)
+#define HSW_PWR_WELL_CTL5 0x45410
+#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
+#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
+#define HSW_PWR_WELL_FORCE_ON (1<<19)
+#define HSW_PWR_WELL_CTL6 0x45414
+
#endif /* _I915_REG_H_ */
--
1.7.9.5
next prev parent reply other threads:[~2012-03-29 15:32 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-29 15:32 [PATCH 00/41] [RFC] Haswell v2 Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 01/41] drm/i915: transform HAS_PCH_SPLIT in a feature check Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 02/41] drm/i915: add Haswell devices and their PCI IDs Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 03/41] drm/i915: hook Haswell devices in place Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 04/41] drm/i915: add support for LynxPoint PCH Eugeni Dodonov
2012-03-29 15:32 ` Eugeni Dodonov [this message]
2012-03-29 15:32 ` [PATCH 06/41] drm/i915: add enumeration for DDI ports Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 07/41] drm/i915: add DDI registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 08/41] drm/i915: add DP_TP_CTL registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 09/41] drm/i915: add DP_TP_STATUS registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 10/41] drm/i915: add definitions for DDI_BUF_CTL registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 11/41] drm/i915: add definition of DDI buffer translations regs Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 12/41] drm/i915: add definition of LPT FDI port width registers Eugeni Dodonov
2012-03-29 20:25 ` Daniel Vetter
2012-03-29 15:32 ` [PATCH 13/41] drm/i915: add SBI registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 14/41] drm/i915: add support for SBI ops Eugeni Dodonov
2012-03-29 20:27 ` Daniel Vetter
2012-03-29 15:32 ` [PATCH 15/41] drm/i915: add PIXCLK_GATE register Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 16/41] drm/i915: add S PLL control Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 17/41] drm/i915: add port clock selection support for HSW Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 18/41] drm/i915: add SSC offsets for SBI access Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 19/41] drm/i915: add LCPLL control registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 20/41] drm/i915: add WRPLL clocks Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 21/41] drm/i915: add WM_LINETIME registers Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 22/41] drm/i915: add SFUSE_STRAP registers for digital port detection Eugeni Dodonov
2012-03-29 20:35 ` Daniel Vetter
2012-03-29 15:32 ` [PATCH 23/41] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 24/41] drm/i915: share forcewaking code between IVB and HSW Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 25/41] drm/i915: haswell has 3 pipes as well Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 26/41] drm/i915: reuse Ivybridge interrupts code for Haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 27/41] drm/i915: share pipe count handling with Ivybridge Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 28/41] drm/i915: share IVB cursor routine with Haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 29/41] drm/i915: show unknown sdvox registers on hdmi init Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 30/41] drm/i915: enable power wells on haswell init Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 31/41] drm/i915: disable rc6 on haswell for now Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 32/41] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 33/41] drm/i915: initialize DDI buffer translations Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 34/41] drm/i915: perform Haswell DDI link training in FDI mode Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 35/41] drm/i915: disable pipe DDI function when disabling pipe Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 36/41] drm/i915: do not use fdi_normal_train on haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 37/41] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 38/41] drm/i915: detect digital outputs on Haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 39/41] drm/i915: add support for DDI-controlled digital outputs Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 40/41] drm/i915: prepare HDMI link for Haswell Eugeni Dodonov
2012-03-29 15:32 ` [PATCH 41/41] drm/i915: add debugging bits for haswell modesetting Eugeni Dodonov
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