From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/2] drm/i915: ring irq cleanups Date: Fri, 30 Mar 2012 09:33:22 +0100 Message-ID: <1333096416_153628@CP5-2952> References: <1333073487-4138-1-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E9089EF0C for ; Fri, 30 Mar 2012 01:33:51 -0700 (PDT) In-Reply-To: <1333073487-4138-1-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Ben Widawsky , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Thu, 29 Mar 2012 19:11:26 -0700, Ben Widawsky wrote: > - gen6 put/get only need one argument > rflags and gflags are always the same (see above explanation) > - remove a couple redundantly defined IRQs > - reordered some lines to make things go in descending order > > Every ring has its own interrupts, enables, masks, and status bits that > are fed into the main interrupt enable/mask/status registers. At one > point in time it seemed like a good idea to make our functions support > the notion that each interrupt may have a different bit position in the > corresponding register (blitter parser error may be bit n in IMR, but > bit m in blitter IMR). It turned out though that the HW designers did us > a solid on Gen6+ and this unfortunate situation has been avoided. This > allows our interrupt code to be cleaned up a bit. > > I jammed this into one commit because there should be no functional > change with this commit, and staging it into multiple commits was > unnecessarily artificial IMO. > > CC: Chris Wilson > CC: Jesse Barnes > Signed-off-by: Ben Widawsky Those two patches are Reviewed-by: Chris Wilson We can go further in simplifying get/put irq. First requires a dev_priv->gt.enable_irq() and then refactor the common (pro|epi)logue. -Chris -- Chris Wilson, Intel Open Source Technology Centre