From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: invalidate render cache on gen2 Date: Thu, 19 Apr 2012 15:47:44 +0100 Message-ID: <1334846886_26427@CP5-2952> References: <1334846722-1161-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 00F219EBBC for ; Thu, 19 Apr 2012 07:48:11 -0700 (PDT) In-Reply-To: <1334846722-1161-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Thu, 19 Apr 2012 16:45:22 +0200, Daniel Vetter wrote: > It looks like we also need to flush the render cache when we just > invalidate it. This fixes a regression in i-g-t/gem_tiled_blits on my > i855gm. I guess the render cache there is virtually indexed, so we > need to clean it when changing gtt mappings. > > This regression has been introduce in > > commit 46f0f8d120c4afae53a5670bf3ac80a928340ff3 > Author: Chris Wilson > Date: Wed Apr 18 11:12:11 2012 +0100 > > drm/i915: Don't set a MBZ bit in gen2/3 MI_FLUSH > > Cc: Chris Wilson > Signed-Off-by: Daniel Vetter My fault, with hindsight comes wisdom, Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre