From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 5/6] drm/i915: Handle PendingFlip on gen3 robustly Date: Tue, 24 Apr 2012 21:39:21 +0100 Message-ID: <1335299995_41089@CP5-2952> References: <1335288691-21819-1-git-send-email-chris@chris-wilson.co.uk> <1335288691-21819-5-git-send-email-chris@chris-wilson.co.uk> <20120424125035.6a495e85@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id C73F59E75A for ; Tue, 24 Apr 2012 13:39:58 -0700 (PDT) In-Reply-To: <20120424125035.6a495e85@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 24 Apr 2012 12:50:35 -0700, Jesse Barnes wrote: > > + /* "flip pending" bit means done if this bit is set */ > > + I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); > > + > > Aha. I hope this works across platforms. I don't even know why this > bit exists, so I hope it's safe to change on a given chipset & platform. Patch splitting to come. So far I've tested on a 945gm and PineView and both are happy with the legacy PendingFlip status mode. And Daniel has tested on a 915g which was demonstrating the same trouble as our dear bugzilla reporter. One person I'd like to see I can get testing is Simon Farnsworth if he still has only of his 945s available for testing. -Chris -- Chris Wilson, Intel Open Source Technology Centre