From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: use the new masked bit macro some more Date: Thu, 26 Apr 2012 20:40:21 +0100 Message-ID: <1335469258_60890@CP5-2952> References: <1335466270_60498@CP5-2952> <1335468782-19796-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 68DEB9EB43 for ; Thu, 26 Apr 2012 12:41:04 -0700 (PDT) In-Reply-To: <1335468782-19796-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Thu, 26 Apr 2012 21:33:02 +0200, Daniel Vetter wrote: > /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ > if (IS_GEN3(dev)) { > - u32 tmp = I915_READ(MI_ARB_STATE); > - if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { > - /* arb state is a masked write, so set bit + bit in mask */ > - tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); > + if (!(I915_READ(MI_ARB_STATE) & MI_ARB_C3_LP_WRITE_ENABLE)) { > + u32 tmp = _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE); > I915_WRITE(MI_ARB_STATE, tmp); Just write the masked bit, the state before is irrelevant. I can't spot any other shifts that look to be being used as a mask, so whatever the outcome of the above bikeshedding: Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre