From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 03/12] drm/i915: implement ironlake_wait_for_vblank Date: Thu, 03 May 2012 13:00:54 +0100 Message-ID: <1336046455_129602@CP5-2952> References: <1336010154-2946-1-git-send-email-przanoni@gmail.com> <1336010154-2946-3-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id F018DA0B54 for ; Thu, 3 May 2012 05:01:02 -0700 (PDT) In-Reply-To: <1336010154-2946-3-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, 2 May 2012 22:55:45 -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > intel_wait_for_vblank uses PIPESTAT, which does not exist on Ironlake > and newer. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 613f871..a2617b2 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -806,6 +806,32 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, > return true; > } > > +static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + u32 vblank_start, line; > + u32 dsl_reg = PIPEDSL(pipe); > + u32 pipeconf = I915_READ(PIPECONF(pipe)); > + > + if (!((pipeconf & PIPECONF_ENABLE) && > + (pipeconf & I965_PIPECONF_ACTIVE))) > + return; > + > + vblank_start = I915_READ(VBLANK(pipe)) & 0x1FFF; > + > + if (pipeconf & PIPECONF_INTERLACE_MASK) > + vblank_start >>= 1; > + > + line = I915_READ(dsl_reg) & DSL_LINEMASK_GEN3; > + > + if (line >= vblank_start) > + return; The caller expects for at least 1 frame to have passed, the documentation tends to refer to the registers being latched until the next vblank. As we don't know precisely when those registers are copied, we need to wait one complete cycle to be sure that we don't return too early. Or maybe I'm being too paranoid. Actually, with modesetting one can never be too paranoid. -Chris -- Chris Wilson, Intel Open Source Technology Centre