From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 09/14] drm/i915: disable the infoframe before changing it Date: Fri, 4 May 2012 17:18:21 -0300 Message-ID: <1336162707-3504-8-git-send-email-przanoni@gmail.com> References: <1336010154-2946-1-git-send-email-przanoni@gmail.com> <1336162707-3504-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-vx0-f177.google.com (mail-vc0-f177.google.com [209.85.220.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 65075A0D68 for ; Fri, 4 May 2012 13:18:46 -0700 (PDT) Received: by mail-vx0-f177.google.com with SMTP id f13so2936287vcb.36 for ; Fri, 04 May 2012 13:18:46 -0700 (PDT) In-Reply-To: <1336162707-3504-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni That's what the VIDEO_DIP_CTL documentation says we need to do. Except when it's the AVI InfoFrame and we're ironlake_write_infoframe. Signed-off-by: Paulo Zanoni Reviewed-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_hdmi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 57ab62f..6e1086d 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -167,6 +167,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + val &= ~intel_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(VIDEO_DIP_CTL, val); @@ -199,6 +200,13 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + /* The DIP control register spec says that we need to update the AVI + * infoframe without clearing its enable bit */ + if (frame->type == DIP_TYPE_AVI) + val |= VIDEO_DIP_ENABLE_AVI; + else + val &= ~intel_infoframe_enable(frame); + val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -231,6 +239,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + val &= ~intel_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); -- 1.7.10