From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH 2/2] drm/i915: Enable the PCH PLL for all
	generations after link training
Date: Sun, 13 May 2012 15:25:10 +0100
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To: Daniel Vetter <daniel@ffwll.ch>, Eugeni Dodonov <eugeni@dodonov.net>, Jesse Barnes <jbarnes@virtuousgeek.org>
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On Sun, 13 May 2012 16:08:32 +0200, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Sun, May 13, 2012 at 09:54:09AM +0100, Chris Wilson wrote:
> > Hidden away within one chipset specific path was the necessary logic to
> > turn on the PLL. This needs to be done everywhere in order for us to
> > drive any display! As such as soon as we tested on a non-CougarPoint
> > chipset, we failed to bring up any DisplayPorts and generated a nice set
> > of assertion failures in the process. At least one part of our logic is
> > working, the part that assumes that we have no idea what we are doing.
> > 
> > Reported-by: guang.a.yang@intel.com
> > References: https://bugs.freedesktop.org/show_bug.cgi?id=49712
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
> 
> I guess as-is this patch will blow up on hsw. I think we need to change
> the BUG_ON(!pll) in there into a return, like in the disable code. Eugeni?

Whoops, should have looked harder. My thinking was that on hsw, the pll
would be NULL and so the routine would have no effect. Tricksy BUG_ON.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre