From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: fix hard-hangs while resetting the gpu on some ilks Date: Tue, 19 Jun 2012 15:10:45 +0100 Message-ID: <1340115069_14722@CP5-2952> References: <1340115330-1842-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id 24AF59E841 for ; Tue, 19 Jun 2012 07:11:16 -0700 (PDT) In-Reply-To: <1340115330-1842-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Tue, 19 Jun 2012 16:15:30 +0200, Daniel Vetter wrote: > Now I still think that having unified hw frobbing paths between driver > load, resume and gpu reset is highly desirable, so I've opted to just > add a reset argument to disable the offending code for gpu resets. I > have no idea why it actually blows up. Did you look at whether it was an IRQ firing during the reset may have been an issue? One of the patches I have is to disable interrupts across the hw reset during i915_reset(). Otherwise, bisect the register writes int the offending ironlake_enable_drps(). -Chris -- Chris Wilson, Intel Open Source Technology Centre