From mboxrd@z Thu Jan 1 00:00:00 1970 From: Eugeni Dodonov Subject: [PATCH 05/21] drm/i915: Disable DDI Pipe Control on HSW while disabling pipe Date: Thu, 28 Jun 2012 15:55:33 -0300 Message-ID: <1340909749-15249-6-git-send-email-eugeni.dodonov@intel.com> References: <1340909749-15249-1-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id AADD5A0933 for ; Thu, 28 Jun 2012 11:54:16 -0700 (PDT) In-Reply-To: <1340909749-15249-1-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Eugeni Dodonov List-Id: intel-gfx@lists.freedesktop.org From: Shobhit Kumar In Haswell while disabling a pipe, we need to disable the DDI control as well along with the PIPECONF. Otherwise we will hit assertions during crtc disable Signed-off-by: Shobhit Kumar Signed-off-by: Eugeni Dodonov --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 3fbc802..28bee8a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1794,6 +1794,13 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, I915_WRITE(reg, val & ~PIPECONF_ENABLE); intel_wait_for_pipe_off(dev_priv->dev, pipe); + + /* On HSW DDI Pipe control has to be disabled as well */ + if (IS_HASWELL(dev_priv->dev)) { + val = I915_READ(DDI_FUNC_CTL(pipe)); + val = val & (~PIPE_DDI_FUNC_ENABLE); + I915_WRITE(DDI_FUNC_CTL(pipe), val); + } } /* -- 1.7.11.1