From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 08/09] drm/i915: fix DP AUX register definitions on Haswell Date: Fri, 29 Jun 2012 16:03:40 -0300 Message-ID: <1340996621-14345-8-git-send-email-przanoni@gmail.com> References: <1340996621-14345-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BEC79A0B90 for ; Fri, 29 Jun 2012 12:04:53 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f11so3283731ghb.36 for ; Fri, 29 Jun 2012 12:04:53 -0700 (PDT) In-Reply-To: <1340996621-14345-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni The old rule that the AUX registers are just an offset (+4 and +10) from output_reg is not true anymore, since output_reg in on the CPU and some AUX regs are on the PCH. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_dp.c | 21 +++++++++++++++++++++ 2 files changed, 29 insertions(+) The previous patch series didn't need this patch because they were calling intel_dp_init with PCH_DP_B as the second argument. IMHO this is ugly because PCH_DP_B does not exist on Haswell. This value will become intel_dp->output_reg and then eventually some functions will even write to it. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f28f2b2..475ada8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2493,6 +2493,14 @@ #define DPD_AUX_CH_DATA4 0x64320 #define DPD_AUX_CH_DATA5 0x64324 +#define PCH_DPB_AUX_CH_CTL 0xe4110 +#define PCH_DPC_AUX_CH_CTL 0xe4210 +#define PCH_DPD_AUX_CH_CTL 0xe4310 + +#define PCH_DPB_AUX_CH_DATA 0xe4114 +#define PCH_DPC_AUX_CH_DATA 0xe4214 +#define PCH_DPD_AUX_CH_DATA 0xe4314 + #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31) #define DP_AUX_CH_CTL_DONE (1 << 30) #define DP_AUX_CH_CTL_INTERRUPT (1 << 29) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 287bef9..22dae6d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -356,6 +356,27 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, uint32_t aux_clock_divider; int try, precharge; + if (IS_HASWELL(dev)) { + switch (intel_dp->port) { + case PORT_A: + ch_ctl = DPA_AUX_CH_CTL; + ch_data = DPA_AUX_CH_DATA1; + break; + case PORT_B: + ch_ctl = PCH_DPB_AUX_CH_CTL; + ch_data = PCH_DPB_AUX_CH_DATA; + break; + case PORT_C: + ch_ctl = PCH_DPC_AUX_CH_CTL; + ch_data = PCH_DPC_AUX_CH_DATA; + break; + case PORT_D: + ch_ctl = PCH_DPD_AUX_CH_CTL; + ch_data = PCH_DPD_AUX_CH_DATA; + break; + } + } + intel_dp_check_edp(intel_dp); /* The clock divider is based off the hrawclk, * and would like to run at 2MHz. So, take the -- 1.7.10.2