From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 0/8] Haswell HDMI fixes Date: Wed, 8 Aug 2012 14:15:26 -0300 Message-ID: <1344446134-3704-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-yx0-f177.google.com (mail-yx0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 27E14A09CB for ; Wed, 8 Aug 2012 10:15:53 -0700 (PDT) Received: by yenr9 with SMTP id r9so1099933yen.36 for ; Wed, 08 Aug 2012 10:15:52 -0700 (PDT) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni HDMI already works fine on Haswell, but we still have room for improvements. This series will make us less dependent on the bits set by the BIOS, will fix cases where DVI was not working and will also improve the cases where we have 2 HDMI monitors. - Patches 1-4 are all about the DDI_FUNC_CTL register. - Patch 5 is to satisfy my OCD. - Patch 6 was spotted while writing patch 5. - Patches 7-8 are about setting PLLs. Paulo Zanoni (8): drm/i915: fix pipe DDI mode select drm/i915: set the DDI sync polarity bits drm/i915: correctly set the DDI_FUNC_CTL bpc field drm/i915: completely reset the value of DDI_FUNC_CTL drm/i915: reindent Haswell register definitions drm/i915: add parentheses around PIXCLK_GATE definitions drm/i915: try harder to find WR PLL clock settings drm/i915: try to use WR PLL 2 drivers/gpu/drm/i915/i915_reg.h | 184 ++++++++++++++++++--------------------- drivers/gpu/drm/i915/intel_ddi.c | 108 ++++++++++++++++------- 2 files changed, 163 insertions(+), 129 deletions(-) -- 1.7.11.2