From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Apply post-sync write for pipe control invalidates Date: Fri, 10 Aug 2012 11:07:47 +0100 Message-ID: <1344593270_68850@CP5-2952> References: <1344589505-4835-1-git-send-email-chris@chris-wilson.co.uk> <1344590290-5206-1-git-send-email-chris@chris-wilson.co.uk> <87d32zjcgo.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from fireflyinternet.com (smtp.fireflyinternet.com [109.228.6.236]) by gabe.freedesktop.org (Postfix) with ESMTP id D801A9E79A for ; Fri, 10 Aug 2012 03:07:54 -0700 (PDT) In-Reply-To: <87d32zjcgo.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 10 Aug 2012 12:57:59 +0300, Jani Nikula wrote: > On Fri, 10 Aug 2012, Chris Wilson wrote: > > When invalidating the TLBs it is documentated as requiring a post-sync > > write. Failure to do so seems to result in a GPU hang. > > > > Exposure to this hang on IVB seems to be a result of removing the extra > > stalls required for SNB pipecontrol workarounds: > > Hi Chris, AFAICT TLB invalidate requires PIPE_CONTROL_CS_STALL set per > the spec. I can't find a mention of the post-sync write, though. Could > you double check, please? Considering replacing it with a CS_STALL just hard hung my box, I remain unconvinced. :-p -Chris -- Chris Wilson, Intel Open Source Technology Centre