Re: [PATCH 07/10] drm/i915: completely rewrite the Haswell PLL handling code

Lespiau, Damien
2012-10-10T14:22:03Z

On Fri, Oct 5, 2012 at 4:05 PM, Paulo Zanoni <przanoni@gmail.com> wrote:
> + val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SCC;

We probably want a patch on top to fix the SCC typo (should be SSC,
Spread Spectrum Clock).

There's also some fiddly bit with CPU Vs PCH SSC sources, but this can
be a later addition.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

--
Damien