From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 35/47] drm/i915: set the correct eDP aux channel clock divider on DDI Date: Tue, 2 Oct 2012 17:52:10 -0300 Message-ID: <1349211142-4802-36-git-send-email-przanoni@gmail.com> References: <1349211142-4802-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gg0-f177.google.com (mail-gg0-f177.google.com [209.85.161.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 6EFE89EF7D for ; Tue, 2 Oct 2012 13:53:57 -0700 (PDT) Received: by mail-gg0-f177.google.com with SMTP id m2so1762342ggn.36 for ; Tue, 02 Oct 2012 13:53:57 -0700 (PDT) In-Reply-To: <1349211142-4802-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni The cdclk frequency is not always the same, so the value here should be adjusted to match it. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_dp.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 2e4e588..cc9e5ab 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -351,7 +351,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, int i; int recv_bytes; uint32_t status; - uint32_t aux_clock_divider; + uint32_t aux_clock_divider, cdclk_freq; int try, precharge; if (IS_HASWELL(dev)) { @@ -387,7 +387,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, * clock divider. */ if (is_cpu_edp(intel_dp)) { - if (IS_VALLEYVIEW(dev)) + if (IS_HASWELL(dev)) { + cdclk_freq = I915_READ(CDCLK_FREQ) & CDCLK_FREQ_MASK; + aux_clock_divider = (cdclk_freq + 1) >> 1; + } else if (IS_VALLEYVIEW(dev)) aux_clock_divider = 100; else if (IS_GEN6(dev) || IS_GEN7(dev)) aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ -- 1.7.10.4