[PATCH 32/47] drm/i915: convert pipe timing definitions to transcoder

Paulo Zanoni
2012-10-02T20:53:51Z

drivers/gpu/drm/i915/i915_irq.c | 7 +++--
drivers/gpu/drm/i915/i915_reg.h | 14 +++++-----
drivers/gpu/drm/i915/intel_crt.c | 6 ++--
drivers/gpu/drm/i915/intel_display.c | 51 +++++++++++++++++-----------------
4 files changed, 40 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 024b08d..09b3551 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
int vbl_start, vbl_end, htotal, vtotal;
bool in_vbl = true;
int ret = 0;
+ enum transcoder transcoder = pipe_to_transcoder(dev_priv, pipe);

if (!i915_pipe_enabled(dev, pipe)) {
DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
@@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
}

/* Get vtotal. */
- vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
+ vtotal = 1 + ((I915_READ(VTOTAL(transcoder)) >> 16) & 0x1fff);

if (INTEL_INFO(dev)->gen >= 4) {
/* No obvious pixelcount register. Only query vertical
@@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
*/
position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;

- htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
+ htotal = 1 + ((I915_READ(HTOTAL(transcoder)) >> 16) & 0x1fff);
*vpos = position / htotal;
*hpos = position - (*vpos * htotal);
}

/* Query vblank area. */
- vbl = I915_READ(VBLANK(pipe));
+ vbl = I915_READ(VBLANK(transcoder));

/* Test position against vblank region. */
vbl_start = vbl & 0x1fff;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4715754..3b91031 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1561,14 +1561,14 @@
#define _VSYNCSHIFT_B 0x61028

-#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
-#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
-#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
-#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
-#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
-#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
+#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
+#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
+#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
+#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
+#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
+#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
-#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
+#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)

/* VGA port control */
#define ADPA 0x61100
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index bc2a91f..4f32ea9 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -484,9 +484,9 @@ intel_crt_load_detect(struct intel_crt *crt)
DRM_DEBUG_KMS("starting load-detect on CRT\n");

bclrpat_reg = BCLRPAT(pipe);
- vtotal_reg = VTOTAL(pipe);
- vblank_reg = VBLANK(pipe);
- vsync_reg = VSYNC(pipe);
+ vtotal_reg = VTOTAL(transcoder);
+ vblank_reg = VBLANK(transcoder);
+ vsync_reg = VSYNC(transcoder);
pipeconf_reg = PIPECONF(transcoder);
pipe_dsl_reg = PIPEDSL(pipe);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index aa5cc84..15b2a4f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3019,14 +3019,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)

/* set transcoder timing, panel must allow it */
assert_panel_unlocked(dev_priv, pipe);
- I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
- I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
- I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
+ I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(transcoder)));
+ I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(transcoder)));
+ I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(transcoder)));

- I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
- I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
- I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
- I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
+ I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(transcoder)));
+ I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(transcoder)));
+ I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(transcoder)));
+ I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(transcoder)));

if (!IS_HASWELL(dev))
intel_fdi_normal_train(crtc);
@@ -4338,6 +4338,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
struct drm_device *dev = intel_crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
enum pipe pipe = intel_crtc->pipe;
+ enum transcoder transcoder = intel_crtc->transcoder;
uint32_t vsyncshift;

if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -4351,25 +4352,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
}

if (INTEL_INFO(dev)->gen > 3)
- I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
+ I915_WRITE(VSYNCSHIFT(transcoder), vsyncshift);

- I915_WRITE(HTOTAL(pipe),
+ I915_WRITE(HTOTAL(transcoder),
(adjusted_mode->crtc_hdisplay - 1) |
((adjusted_mode->crtc_htotal - 1) << 16));
- I915_WRITE(HBLANK(pipe),
+ I915_WRITE(HBLANK(transcoder),
(adjusted_mode->crtc_hblank_start - 1) |
((adjusted_mode->crtc_hblank_end - 1) << 16));
- I915_WRITE(HSYNC(pipe),
+ I915_WRITE(HSYNC(transcoder),
(adjusted_mode->crtc_hsync_start - 1) |
((adjusted_mode->crtc_hsync_end - 1) << 16));

- I915_WRITE(VTOTAL(pipe),
+ I915_WRITE(VTOTAL(transcoder),
(adjusted_mode->crtc_vdisplay - 1) |
((adjusted_mode->crtc_vtotal - 1) << 16));
- I915_WRITE(VBLANK(pipe),
+ I915_WRITE(VBLANK(transcoder),
(adjusted_mode->crtc_vblank_start - 1) |
((adjusted_mode->crtc_vblank_end - 1) << 16));
- I915_WRITE(VSYNC(pipe),
+ I915_WRITE(VSYNC(transcoder),
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));

@@ -6333,12 +6334,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe;
+ enum transcoder transcoder = intel_crtc->transcoder;
struct drm_display_mode *mode;
- int htot = I915_READ(HTOTAL(pipe));
- int hsync = I915_READ(HSYNC(pipe));
- int vtot = I915_READ(VTOTAL(pipe));
- int vsync = I915_READ(VSYNC(pipe));
+ int htot = I915_READ(HTOTAL(transcoder));
+ int hsync = I915_READ(HSYNC(transcoder));
+ int vtot = I915_READ(VTOTAL(transcoder));
+ int vsync = I915_READ(VSYNC(transcoder));

mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode)
@@ -8807,12 +8808,12 @@ intel_display_capture_error_state(struct drm_device *dev)

error->pipe[i].conf = I915_READ(PIPECONF(transcoder));
error->pipe[i].source = I915_READ(PIPESRC(i));
- error->pipe[i].htotal = I915_READ(HTOTAL(i));
- error->pipe[i].hblank = I915_READ(HBLANK(i));
- error->pipe[i].hsync = I915_READ(HSYNC(i));
- error->pipe[i].vtotal = I915_READ(VTOTAL(i));
- error->pipe[i].vblank = I915_READ(VBLANK(i));
- error->pipe[i].vsync = I915_READ(VSYNC(i));
+ error->pipe[i].htotal = I915_READ(HTOTAL(transcoder));
+ error->pipe[i].hblank = I915_READ(HBLANK(transcoder));
+ error->pipe[i].hsync = I915_READ(HSYNC(transcoder));
+ error->pipe[i].vtotal = I915_READ(VTOTAL(transcoder));
+ error->pipe[i].vblank = I915_READ(VBLANK(transcoder));
+ error->pipe[i].vsync = I915_READ(VSYNC(transcoder));
}

return error;
--
1.7.10.4