From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 04/14] drm/i915: add DP support to intel_ddi_disable_port Date: Mon, 15 Oct 2012 15:51:32 -0300 Message-ID: <1350327102-4463-5-git-send-email-przanoni@gmail.com> References: <1350327102-4463-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-gh0-f177.google.com (mail-gh0-f177.google.com [209.85.160.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BA6409F738 for ; Mon, 15 Oct 2012 11:52:10 -0700 (PDT) Received: by mail-gh0-f177.google.com with SMTP id f20so1349193ghb.36 for ; Mon, 15 Oct 2012 11:52:10 -0700 (PDT) In-Reply-To: <1350327102-4463-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni Just a missing register. There is no problem to run this code when the output is HDMI. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 5071370..4f03b1b 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1105,14 +1105,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder) struct drm_i915_private *dev_priv = encoder->dev->dev_private; enum port port = intel_ddi_get_encoder_port(intel_encoder); uint32_t val; + bool wait = false; val = I915_READ(DDI_BUF_CTL(port)); if (val & DDI_BUF_CTL_ENABLE) { val &= ~DDI_BUF_CTL_ENABLE; I915_WRITE(DDI_BUF_CTL(port), val); - intel_wait_ddi_buf_idle(dev_priv, port); + wait = true; } + val = I915_READ(DP_TP_CTL(port)); + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); + val |= DP_TP_CTL_LINK_TRAIN_PAT1; + I915_WRITE(DP_TP_CTL(port), val); + + if (wait) + intel_wait_ddi_buf_idle(dev_priv, port); + I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } -- 1.7.11.4