Re: [PATCH 08/14] drm/i915: convert pipe timing definitions to transcoder

Daniel Vetter
2012-10-18T22:28:11Z

On Thu, Oct 18, 2012 at 06:21:38PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Again, I think we can drop the hunks for the load detect code and the pch
stuff for now. For the pch stuff I think we'll better do that once we give
vga a good look.
-Daniel

> ---
> drivers/gpu/drm/i915/i915_irq.c | 7 ++---
> drivers/gpu/drm/i915/i915_reg.h | 14 +++++-----
> drivers/gpu/drm/i915/intel_crt.c | 6 ++---
> drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++-----------------
> 4 files changed, 41 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index c9b186d..31b266b 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -185,6 +185,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> int vbl_start, vbl_end, htotal, vtotal;
> bool in_vbl = true;
> int ret = 0;
> + enum transcoder cpu_transcoder = pipe_to_cpu_transcoder(dev_priv, pipe);
>
> if (!i915_pipe_enabled(dev, pipe)) {
> DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
> @@ -193,7 +194,7 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> }
>
> /* Get vtotal. */
> - vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
> + vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
>
> if (INTEL_INFO(dev)->gen >= 4) {
> /* No obvious pixelcount register. Only query vertical
> @@ -213,13 +214,13 @@ static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
> */
> position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
>
> - htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
> + htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
> *vpos = position / htotal;
> *hpos = position - (*vpos * htotal);
> }
>
> /* Query vblank area. */
> - vbl = I915_READ(VBLANK(pipe));
> + vbl = I915_READ(VBLANK(cpu_transcoder));
>
> /* Test position against vblank region. */
> vbl_start = vbl & 0x1fff;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5b4f608..f22059e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1565,14 +1565,14 @@
> #define _VSYNCSHIFT_B 0x61028
>
>
> -#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
> -#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
> -#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
> -#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
> -#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
> -#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
> +#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
> +#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
> +#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
> +#define VTOTAL(trans) _TRANSCODER(trans, _VTOTAL_A, _VTOTAL_B)
> +#define VBLANK(trans) _TRANSCODER(trans, _VBLANK_A, _VBLANK_B)
> +#define VSYNC(trans) _TRANSCODER(trans, _VSYNC_A, _VSYNC_B)
> #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
> -#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
> +#define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
>
> /* VGA port control */
> #define ADPA 0x61100
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 2a2c976..6e96ba6 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -488,9 +488,9 @@ intel_crt_load_detect(struct intel_crt *crt)
> DRM_DEBUG_KMS("starting load-detect on CRT\n");
>
> bclrpat_reg = BCLRPAT(pipe);
> - vtotal_reg = VTOTAL(pipe);
> - vblank_reg = VBLANK(pipe);
> - vsync_reg = VSYNC(pipe);
> + vtotal_reg = VTOTAL(cpu_transcoder);
> + vblank_reg = VBLANK(cpu_transcoder);
> + vsync_reg = VSYNC(cpu_transcoder);
> pipeconf_reg = PIPECONF(cpu_transcoder);
> pipe_dsl_reg = PIPEDSL(pipe);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 95a4a5f..9202cb6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3019,14 +3019,15 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>
> /* set transcoder timing, panel must allow it */
> assert_panel_unlocked(dev_priv, pipe);
> - I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
> - I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
> - I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
> + I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(cpu_transcoder)));
> + I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(cpu_transcoder)));
> + I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(cpu_transcoder)));
>
> - I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
> - I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
> - I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
> - I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
> + I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
> + I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(cpu_transcoder)));
> + I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(cpu_transcoder)));
> + I915_WRITE(TRANS_VSYNCSHIFT(pipe),
> + I915_READ(VSYNCSHIFT(cpu_transcoder)));
>
> if (!IS_HASWELL(dev))
> intel_fdi_normal_train(crtc);
> @@ -4339,6 +4340,7 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
> struct drm_device *dev = intel_crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> enum pipe pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> uint32_t vsyncshift;
>
> if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -4352,25 +4354,25 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
> }
>
> if (INTEL_INFO(dev)->gen > 3)
> - I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
> + I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
>
> - I915_WRITE(HTOTAL(pipe),
> + I915_WRITE(HTOTAL(cpu_transcoder),
> (adjusted_mode->crtc_hdisplay - 1) |
> ((adjusted_mode->crtc_htotal - 1) << 16));
> - I915_WRITE(HBLANK(pipe),
> + I915_WRITE(HBLANK(cpu_transcoder),
> (adjusted_mode->crtc_hblank_start - 1) |
> ((adjusted_mode->crtc_hblank_end - 1) << 16));
> - I915_WRITE(HSYNC(pipe),
> + I915_WRITE(HSYNC(cpu_transcoder),
> (adjusted_mode->crtc_hsync_start - 1) |
> ((adjusted_mode->crtc_hsync_end - 1) << 16));
>
> - I915_WRITE(VTOTAL(pipe),
> + I915_WRITE(VTOTAL(cpu_transcoder),
> (adjusted_mode->crtc_vdisplay - 1) |
> ((adjusted_mode->crtc_vtotal - 1) << 16));
> - I915_WRITE(VBLANK(pipe),
> + I915_WRITE(VBLANK(cpu_transcoder),
> (adjusted_mode->crtc_vblank_start - 1) |
> ((adjusted_mode->crtc_vblank_end - 1) << 16));
> - I915_WRITE(VSYNC(pipe),
> + I915_WRITE(VSYNC(cpu_transcoder),
> (adjusted_mode->crtc_vsync_start - 1) |
> ((adjusted_mode->crtc_vsync_end - 1) << 16));
>
> @@ -6333,12 +6335,12 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> + enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
> struct drm_display_mode *mode;
> - int htot = I915_READ(HTOTAL(pipe));
> - int hsync = I915_READ(HSYNC(pipe));
> - int vtot = I915_READ(VTOTAL(pipe));
> - int vsync = I915_READ(VSYNC(pipe));
> + int htot = I915_READ(HTOTAL(cpu_transcoder));
> + int hsync = I915_READ(HSYNC(cpu_transcoder));
> + int vtot = I915_READ(VTOTAL(cpu_transcoder));
> + int vsync = I915_READ(VSYNC(cpu_transcoder));
>
> mode = kzalloc(sizeof(*mode), GFP_KERNEL);
> if (!mode)
> @@ -8809,12 +8811,12 @@ intel_display_capture_error_state(struct drm_device *dev)
>
> error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
> error->pipe[i].source = I915_READ(PIPESRC(i));
> - error->pipe[i].htotal = I915_READ(HTOTAL(i));
> - error->pipe[i].hblank = I915_READ(HBLANK(i));
> - error->pipe[i].hsync = I915_READ(HSYNC(i));
> - error->pipe[i].vtotal = I915_READ(VTOTAL(i));
> - error->pipe[i].vblank = I915_READ(VBLANK(i));
> - error->pipe[i].vsync = I915_READ(VSYNC(i));
> + error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
> + error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
> + error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
> + error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
> + error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
> + error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
> }
>
> return error;
> --
> 1.7.11.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch