From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 11/36] drm/i915: properly program FDI_RX_MISC pwrdn lane values on HSW Date: Wed, 31 Oct 2012 18:12:30 -0200 Message-ID: <1351714375-15284-12-git-send-email-przanoni@gmail.com> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ye0-f177.google.com (mail-ye0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTP id 9BCDFA0A19 for ; Wed, 31 Oct 2012 13:13:29 -0700 (PDT) Received: by mail-ye0-f177.google.com with SMTP id r1so354583yen.36 for ; Wed, 31 Oct 2012 13:13:29 -0700 (PDT) In-Reply-To: <1351714375-15284-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni That's what our mode set sequence documentation says we need to do. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_ddi.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 5d33f62..0239888 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -205,6 +205,12 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) POSTING_READ(_FDI_RXA_CTL); udelay(100); + /* Program FDI_RX_MISC pwrdn lanes */ + temp = I915_READ(_FDI_RXA_MISC); + temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); + I915_WRITE(_FDI_RXA_MISC, temp); + POSTING_READ(_FDI_RXA_MISC); + temp = I915_READ(DP_TP_STATUS(PORT_E)); if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { DRM_DEBUG_DRIVER("BUF_CTL training done on %d step\n", i); @@ -227,6 +233,14 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) rx_ctl_val &= ~FDI_RX_PLL_ENABLE; I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); + + temp = I915_READ(_FDI_RXA_MISC); + temp &= ~(FDI_RX_PWRDN_LANE1_MASK | + FDI_RX_PWRDN_LANE0_MASK); + temp |= FDI_RX_PWRDN_LANE1_VAL(2) | + FDI_RX_PWRDN_LANE0_VAL(2); + I915_WRITE(_FDI_RXA_MISC, temp); + continue; } } -- 1.7.11.4