From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 18/36] drm/i915: don't write FDI_RX_TUSIZE on lpt_pch_enable Date: Wed, 31 Oct 2012 18:12:37 -0200 Message-ID: <1351714375-15284-19-git-send-email-przanoni@gmail.com> References: <1351714375-15284-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-yh0-f49.google.com (mail-yh0-f49.google.com [209.85.213.49]) by gabe.freedesktop.org (Postfix) with ESMTP id E3F38A0AE2 for ; Wed, 31 Oct 2012 13:13:40 -0700 (PDT) Received: by mail-yh0-f49.google.com with SMTP id j52so347219yhj.36 for ; Wed, 31 Oct 2012 13:13:40 -0700 (PDT) In-Reply-To: <1351714375-15284-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This is done way earlier on HSW/LPT and is just wrong here. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ee81932..f9441d1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3142,11 +3142,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc) assert_transcoder_disabled(dev_priv, pipe); - /* Write the TU size bits before fdi link training, so that error - * detection works. */ - I915_WRITE(FDI_RX_TUSIZE1(pipe), - I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); - /* XXX: pch pll's can be enabled any time before we enable the PCH * transcoder, and we actually should do this to not upset any PCH * transcoder that already use the clock when we share it. -- 1.7.11.4