From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mika Kuoppala Subject: [PATCH 0/6] ring seqno wrap handling Date: Tue, 4 Dec 2012 15:11:59 +0200 Message-ID: <1354626725-8521-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id BCD47E6333 for ; Tue, 4 Dec 2012 05:12:12 -0800 (PST) List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Hi, As Ben suggested, explicitly syncing across wrap boundary revealed yet another set of issues that gem_stress didn't find. So here is a patchset which addresses the syncing problems across wrap boundary. Chris helped me to carve out seqno handling ugliness from my initial attempts to handle the ring wrapping. As I can't break this anymore, i added 6/6. --Mika Mika Kuoppala (6): drm/i915: Add debugfs entry to read/write next_seqno drm/i915: Fix debugfs seqno info print to use uint drm/i915: Don't emit semaphore wait if wrap happened drm/i915: Split intel_ring_begin drm/i915: Add intel_ring_handle_seqno wrap drm/i915: Set initial seqno value close to wrap boundary drivers/gpu/drm/i915/i915_debugfs.c | 88 ++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_gem.c | 6 ++- drivers/gpu/drm/i915/intel_ringbuffer.c | 72 +++++++++++++++++++------ drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- 4 files changed, 148 insertions(+), 20 deletions(-) -- 1.7.9.5