From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 1/7] drm/i915: don't send DP idle pattern before normal pattern on HSW
Date: Fri, 25 Jan 2013 16:59:10 -0200 [thread overview]
Message-ID: <1359140356-4050-2-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1359140356-4050-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Previously I sent "drm/i915: don't read DP_TP_STATUS(PORT_A)", but
after some more discussion I was told by a hardware engineer that we
don't really need to send the idle patterns before the normal pattern
in our current code: we only need this for a DP mode that we currently
don't support. So for now, just kill the whole code. I've already
asked for an update on the documentation, so at some point this code
should match the docs.
This solves "Timed out waiting for DP idle patterns" and "unclaimed
register" messages on eDP.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 51fd797..f2fa219 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1785,16 +1785,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
case DP_TRAINING_PATTERN_DISABLE:
- temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
- I915_WRITE(DP_TP_CTL(port), temp);
-
- if (wait_for((I915_READ(DP_TP_STATUS(port)) &
- DP_TP_STATUS_IDLE_DONE), 1))
- DRM_ERROR("Timed out waiting for DP idle patterns\n");
-
- temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
-
break;
case DP_TRAINING_PATTERN_1:
temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
--
1.7.10.4
next prev parent reply other threads:[~2013-01-25 18:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-25 18:59 [PATCH 0/7] Unclaimed registers and power well V2 Paulo Zanoni
2013-01-25 18:59 ` Paulo Zanoni [this message]
2013-01-26 16:53 ` [PATCH 1/7] drm/i915: don't send DP idle pattern before normal pattern on HSW Daniel Vetter
2013-01-25 18:59 ` [PATCH 2/7] drm/i915: fix intel_init_power_wells Paulo Zanoni
2013-01-26 16:54 ` Daniel Vetter
2013-01-25 18:59 ` [PATCH 3/7] drm/i915: dynamic Haswell display power well support Paulo Zanoni
2013-01-25 18:59 ` [PATCH 4/7] drm/i915: only disable enabled planes on intel_fb_restore_mode Paulo Zanoni
2013-01-25 18:59 ` [PATCH 5/7] drm/i915: check the power down well on assert_pipe() Paulo Zanoni
2013-01-27 23:27 ` Daniel Vetter
2013-01-25 18:59 ` [PATCH 6/7] drm/i915: turn on the power well before suspending Paulo Zanoni
2013-01-25 18:59 ` [PATCH 7/7] drm/i915: set TRANSCODER_EDP even earlier Paulo Zanoni
2013-01-26 16:57 ` Daniel Vetter
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