From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 03/22] drm/i915: add UCGCTL4 to display reg check on VLV Date: Sat, 2 Feb 2013 13:56:07 +0100 Message-ID: <1359809786-26434-4-git-send-email-jbarnes@virtuousgeek.org> References: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy12-pub.bluehost.com (oproxy12-pub.bluehost.com [50.87.16.10]) by gabe.freedesktop.org (Postfix) with SMTP id 6109FE5DC3 for ; Sat, 2 Feb 2013 04:56:41 -0800 (PST) Received: from [151.216.70.136] (port=59537 helo=jbarnes-t420.intel.com) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1U1ce8-0006Th-KX for intel-gfx@lists.freedesktop.org; Sat, 02 Feb 2013 05:56:40 -0700 In-Reply-To: <1359809786-26434-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Add a few regs needed for various clock gating init purposes and make sure they don't fall into the display offset range on VLV. Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 69d0637..13b9b4f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg) case GEN7_HALF_SLICE_CHICKEN1: case GEN6_MBCTL: case GEN6_UCGCTL2: + case GEN7_UCGCTL4: return false; default: break; -- 1.7.9.5