From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: [PATCH 4/8] drm/i915: rip out superflous is_dp&is_cpu_edp tracking Date: Fri, 22 Feb 2013 01:00:44 +0100 Message-ID: <1361491248-14059-5-git-send-email-daniel.vetter@ffwll.ch> References: <1361491248-14059-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by gabe.freedesktop.org (Postfix) with ESMTP id C82CCE6201 for ; Thu, 21 Feb 2013 16:01:02 -0800 (PST) Received: by mail-ee0-f54.google.com with SMTP id c41so41976eek.13 for ; Thu, 21 Feb 2013 16:01:02 -0800 (PST) In-Reply-To: <1361491248-14059-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org The only exception left is is_cpu_edp in the haswell modeset code. We need that to assign the cpu transcoder, but we might want to move that eventually into the encoder, too. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 37 +++++++----------------------------- 1 file changed, 7 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 09dda9d..d4efe97 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4475,7 +4475,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, intel_clock_t clock, reduced_clock; u32 dspcntr, pipeconf; bool ok, has_reduced_clock = false, is_sdvo = false; - bool is_lvds = false, is_tv = false, is_dp = false; + bool is_lvds = false, is_tv = false; struct intel_encoder *encoder; const intel_limit_t *limit; int ret; @@ -4494,9 +4494,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, case INTEL_OUTPUT_TVOUT: is_tv = true; break; - case INTEL_OUTPUT_DISPLAYPORT: - is_dp = true; - break; } num_connectors++; @@ -4577,7 +4574,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, /* default to 8bpc */ pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); - if (is_dp) { + if (intel_crtc->config.has_dp_encoder) { if (intel_crtc->config.dither) { pipeconf |= PIPECONF_6BPC | PIPECONF_DITHER_EN | @@ -5338,7 +5335,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, uint32_t dpll; int factor, num_connectors = 0; bool is_lvds = false, is_sdvo = false, is_tv = false; - bool is_dp = false, is_cpu_edp = false; for_each_encoder_on_crtc(dev, crtc, intel_encoder) { switch (intel_encoder->type) { @@ -5354,14 +5350,6 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, case INTEL_OUTPUT_TVOUT: is_tv = true; break; - case INTEL_OUTPUT_DISPLAYPORT: - is_dp = true; - break; - case INTEL_OUTPUT_EDP: - is_dp = true; - if (!intel_encoder_is_pch_edp(&intel_encoder->base)) - is_cpu_edp = true; - break; } num_connectors++; @@ -5393,7 +5381,8 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, } dpll |= DPLL_DVO_HIGH_SPEED; } - if (is_dp && !is_cpu_edp) + if (intel_crtc->config.has_dp_encoder && + intel_crtc->config.has_pch_encoder) dpll |= DPLL_DVO_HIGH_SPEED; /* compute bitmask from p1 value */ @@ -5446,7 +5435,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, intel_clock_t clock, reduced_clock; u32 dpll, fp = 0, fp2 = 0; bool ok, has_reduced_clock = false; - bool is_lvds = false, is_dp = false, is_cpu_edp = false; + bool is_lvds = false; struct intel_encoder *encoder; int ret; bool dither, fdi_config_ok; @@ -5456,14 +5445,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, case INTEL_OUTPUT_LVDS: is_lvds = true; break; - case INTEL_OUTPUT_DISPLAYPORT: - is_dp = true; - break; - case INTEL_OUTPUT_EDP: - is_dp = true; - if (!intel_encoder_is_pch_edp(&encoder->base)) - is_cpu_edp = true; - break; } num_connectors++; @@ -5500,7 +5481,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, drm_mode_debug_printmodeline(mode); /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ - if (!is_cpu_edp) { + if (intel_crtc->config.has_pch_encoder) { struct intel_pch_pll *pll; pll = intel_get_pch_pll(intel_crtc, dpll, fp); @@ -5613,18 +5594,14 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, int pipe = intel_crtc->pipe; int plane = intel_crtc->plane; int num_connectors = 0; - bool is_dp = false, is_cpu_edp = false; + bool is_cpu_edp = false; struct intel_encoder *encoder; int ret; bool dither; for_each_encoder_on_crtc(dev, crtc, encoder) { switch (encoder->type) { - case INTEL_OUTPUT_DISPLAYPORT: - is_dp = true; - break; case INTEL_OUTPUT_EDP: - is_dp = true; if (!intel_encoder_is_pch_edp(&encoder->base)) is_cpu_edp = true; break; -- 1.7.11.4