From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: [PATCH 03/10] drm/i915: fixup 12bpc hdmi dotclock handling Date: Fri, 22 Feb 2013 01:05:00 +0100 Message-ID: <1361491513-14231-6-git-send-email-daniel.vetter@ffwll.ch> References: <1361491513-14231-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 0097FE61C9 for ; Thu, 21 Feb 2013 16:05:35 -0800 (PST) Received: by mail-ee0-f47.google.com with SMTP id e52so41041eek.20 for ; Thu, 21 Feb 2013 16:05:35 -0800 (PST) In-Reply-To: <1361491513-14231-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org We need to multiply the hdmi port dotclock by 1.5x since it's not really a dotclock, but the 10/8 encoding bitclock divided by 10. Also add correct limit checks for the dotclock and reject modes which don't fit. HDMI 1.4 would allow more, but our hw doesn't support that unfortunately :( Somehow I suspect 12bpc hdmi output never really worked - we really need an i-g-t testcase to check all the different pixel modes and outputs. v2: Fixup the adjusted port clock handling - we need to make sure that the fdi link code still gets the real pixelclock. Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_hdmi.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 0e51b2b..27542c9 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -779,6 +779,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); struct drm_device *dev = encoder->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; + int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2; if (intel_hdmi->color_range_auto) { /* See CEA-861-E - 5.1 Default Encoding Parameters */ @@ -796,19 +797,31 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, pipe_config->has_pch_encoder = true; /* - * HDMI is either 12 or 8, so if the display lets 10bpc sneak - * through, clamp it down. Note that only pch_split platforms have 12bpc - * pipes, g4x and vlv only has a 10bpc pipe, all earlier platforms have - * only 8bpc. + * HDMI is either 12 or 8, so if the display lets 10bpc sneak through, + * clamp it down. Note that only pch_split platforms have 12bpc pipes, + * g4x and vlv only has a 10bpc pipe, all earlier platforms have only + * 8bpc. We also need to check that the higher clock still fits within + * limits. On g4x/vlv we still set the pipe bpp to 12bpc, the crtc fixup + * code will then clamp that to 10bpc. */ - if (pipe_config->pipe_bpp > 8*3) { + if (pipe_config->pipe_bpp > 8*3 && clock_12bpc < 225000) { DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); pipe_config->pipe_bpp = 12*3; + + /* Need to adjust the port link by 1.5x for 12bpc. */ + adjusted_mode->clock = clock_12bpc; + pipe_config->pixel_target_clock = + pipe_config->requested_mode.clock; } else { DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); pipe_config->pipe_bpp = 8*3; } + if (adjusted_mode->clock > 225000) { + DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); + return false; + } + return true; } -- 1.7.11.4