From: Paulo Zanoni <przanoni@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 3/4] drm/i915: print Gen5+ CPU/PCH poison interrupts
Date: Fri, 22 Feb 2013 17:05:30 -0300 [thread overview]
Message-ID: <1361563531-4653-4-git-send-email-przanoni@gmail.com> (raw)
In-Reply-To: <1361563531-4653-1-git-send-email-przanoni@gmail.com>
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
This is bad news and shouldn't be happening.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d0f9c47..98a57ed 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -875,6 +875,9 @@ static void err_int_handler(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 err_int = I915_READ(GEN7_ERR_INT);
+ if (err_int & ERR_INT_POISON)
+ DRM_ERROR("Poison interrupt\n");
+
if (err_int & ERR_INT_FIFO_UNDERRUN_A)
if (intel_report_cpu_fifo_underrun(dev, PIPE_A, false))
DRM_ERROR("Pipe A FIFO underrun\n");
@@ -895,6 +898,9 @@ static void serr_int_handler(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
u32 serr_int = I915_READ(SERR_INT);
+ if (serr_int & SERR_INT_POISON)
+ DRM_ERROR("PCH poison interrupt\n");
+
if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
if (intel_report_pch_fifo_underrun(dev, TRANSCODER_A, false))
DRM_ERROR("PCH transcoder A FIFO underrun\n");
@@ -1101,6 +1107,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (de_iir & DE_PIPEB_VBLANK)
drm_handle_vblank(dev, 1);
+ if (de_iir & DE_POISON)
+ DRM_ERROR("Poison interrupt\n");
+
if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
if (intel_report_cpu_fifo_underrun(dev, PIPE_A, false))
DRM_ERROR("Pipe A FIFO underrun\n");
@@ -2247,7 +2256,8 @@ static void ibx_irq_postinstall(struct drm_device *dev)
SDE_GMBUS |
SDE_AUX_MASK |
SDE_TRANSB_FIFO_UNDER |
- SDE_TRANSA_FIFO_UNDER;
+ SDE_TRANSA_FIFO_UNDER |
+ SDE_POISON;
} else {
mask = SDE_HOTPLUG_MASK_CPT |
SDE_GMBUS_CPT |
@@ -2272,7 +2282,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
- DE_PIPEA_FIFO_UNDERRUN;
+ DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
u32 render_irqs;
dev_priv->irq_mask = ~display_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d27320..62cfcea 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -520,6 +520,7 @@
#define ERROR_GEN6 0x040a0
#define GEN7_ERR_INT 0x44040
+#define ERR_INT_POISON (1<<31)
#define ERR_INT_MMIO_UNCLAIMED (1<<13)
#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
@@ -3569,6 +3570,7 @@
#define SDEIER 0xc400c
#define SERR_INT 0xc4040
+#define SERR_INT_POISON (1<<31)
#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
--
1.7.10.4
next prev parent reply other threads:[~2013-02-22 20:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-22 20:05 [PATCH 0/4] FIFO underrun reporting v2 Paulo Zanoni
2013-02-22 20:05 ` [PATCH 1/4] drm/i915: also disable south interrupts when handling them Paulo Zanoni
2013-03-05 19:08 ` Daniel Vetter
2014-05-23 8:13 ` Daniel Vetter
2014-05-23 11:25 ` Paulo Zanoni
2014-05-23 11:43 ` Daniel Vetter
2013-02-22 20:05 ` [PATCH 2/4] drm/i915: report Gen5+ CPU and PCH FIFO underruns Paulo Zanoni
2013-03-28 13:24 ` Daniel Vetter
2013-04-12 20:05 ` Paulo Zanoni
2013-03-28 13:26 ` Daniel Vetter
2013-02-22 20:05 ` Paulo Zanoni [this message]
2013-03-28 13:25 ` [PATCH 3/4] drm/i915: print Gen5+ CPU/PCH poison interrupts Daniel Vetter
2013-02-22 20:05 ` [PATCH 4/4] drm/i915: remove "inline" keyword from ironlake_disable_display_irq Paulo Zanoni
2013-03-28 12:55 ` Daniel Vetter
2013-02-25 12:14 ` [PATCH 0/4] FIFO underrun reporting v2 Ville Syrjälä
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