From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 10/13] drm/i915: fetch PCH PLL state at init time Date: Tue, 2 Apr 2013 10:03:54 -0700 Message-ID: <1364922237-3620-11-git-send-email-jbarnes@virtuousgeek.org> References: <1364922237-3620-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy5-pub.bluehost.com (oproxy5-pub.bluehost.com [67.222.38.55]) by gabe.freedesktop.org (Postfix) with SMTP id E6E85E5CB4 for ; Tue, 2 Apr 2013 10:11:28 -0700 (PDT) Received: from [67.161.37.189] (port=54872 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1UN4dC-0006iJ-OU for intel-gfx@lists.freedesktop.org; Tue, 02 Apr 2013 11:04:22 -0600 In-Reply-To: <1364922237-3620-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org We need to properly track PCH PLL sharing configs, and generally set up PCH PLL state at init time as part of the state readout process. I-told-you-so-by: Daniel Vetter Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8b55427..208dde4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6915,6 +6915,54 @@ static int ironlake_crtc_clock_get(struct drm_crtc *crtc) return clock; } +static bool ironlake_crtc_pll_get(struct drm_crtc *crtc) +{ + struct drm_i915_private *dev_priv = crtc->dev->dev_private; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + u32 dpll_sel; + + if (HAS_PCH_IBX(dev_priv->dev)) + intel_crtc->pch_pll = &dev_priv->pch_plls[intel_crtc->pipe]; + + if (HAS_PCH_CPT(dev_priv->dev)) { + dpll_sel = I915_READ(PCH_DPLL_SEL); + + switch (intel_crtc->pipe) { + case PIPE_A: + if ((dpll_sel & TRANSA_DPLL_ENABLE) && + (dpll_sel & TRANSA_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSA_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_B: + if ((dpll_sel & TRANSB_DPLL_ENABLE) && + (dpll_sel & TRANSB_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSB_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + case PIPE_C: + if ((dpll_sel & TRANSC_DPLL_ENABLE) && + (dpll_sel & TRANSC_DPLLB_SEL)) + intel_crtc->pch_pll = &dev_priv->pch_plls[1]; + else if (dpll_sel & TRANSC_DPLL_ENABLE) + intel_crtc->pch_pll = &dev_priv->pch_plls[0]; + break; + default: + break; + } + } + + if (intel_crtc->pch_pll) { + intel_crtc->pch_pll->refcount++; + intel_crtc->pch_pll->active = 1; + return true; + } + + return false; +} + static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, struct drm_display_mode *mode) { @@ -6943,6 +6991,9 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc, mode->clock = ironlake_crtc_clock_get(crtc); + if (!ironlake_crtc_pll_get(crtc)) + return false; + drm_mode_set_name(mode); return true; -- 1.7.9.5