From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: [PATCH v2] drm/i915: use lower aux clock divider on non-ULT HSW Date: Tue, 9 Apr 2013 08:11:00 +0300 Message-ID: <1365484260-3868-1-git-send-email-jani.nikula@intel.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id B27ABE5C64 for ; Mon, 8 Apr 2013 22:12:17 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org, Paulo Zanoni Cc: jani.nikula@intel.com List-Id: intel-gfx@lists.freedesktop.org Workaround to avoid intermittent aux channel failures, per spec change. v2: Don't mess with cpu dp aux divider (Paulo Zanoni) Signed-off-by: Jani Nikula --- Untested. --- drivers/gpu/drm/i915/intel_dp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 482b5e5..f8474d1 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ else aux_clock_divider = 225; /* eDP input clock at 450Mhz */ - } else if (HAS_PCH_SPLIT(dev)) + } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { + /* Workaround for non-ULT HSW */ + aux_clock_divider = 74; + } else if (HAS_PCH_SPLIT(dev)) { aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); - else + } else { aux_clock_divider = intel_hrawclk(dev) / 2; + } if (IS_GEN6(dev)) precharge = 3; -- 1.7.10.4