From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 1/7] drm/i915: check the power well inside haswell_get_pipe_config Date: Thu, 18 Apr 2013 16:35:40 -0300 Message-ID: <1366313746-3659-2-git-send-email-przanoni@gmail.com> References: <1366313746-3659-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qa0-f42.google.com (mail-qa0-f42.google.com [209.85.216.42]) by gabe.freedesktop.org (Postfix) with ESMTP id A14AEE65A2 for ; Thu, 18 Apr 2013 12:36:46 -0700 (PDT) Received: by mail-qa0-f42.google.com with SMTP id dx4so1821573qab.1 for ; Thu, 18 Apr 2013 12:36:46 -0700 (PDT) In-Reply-To: <1366313746-3659-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This fixes "unclaimed register" messages when booting with eDP only and i915.disable_power_well=1. The error messages were caused by: commit 0e8ffe1bf81b0780cc6229cb38664754dffe8776 Author: Daniel Vetter Date: Thu Mar 28 10:42:00 2013 +0100 drm/i915: add hw state readout/checking for pipe_config Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 02faba0..61636de 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5856,9 +5856,14 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; uint32_t tmp; - tmp = I915_READ(PIPECONF(crtc->config.cpu_transcoder)); + if (!intel_using_power_well(dev_priv->dev) && + cpu_transcoder != TRANSCODER_EDP) + return false; + + tmp = I915_READ(PIPECONF(cpu_transcoder)); if (!(tmp & PIPECONF_ENABLE)) return false; -- 1.7.10.4