From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 3/7] drm/i915: add intel_display_power_enabled Date: Thu, 18 Apr 2013 16:35:42 -0300 Message-ID: <1366313746-3659-4-git-send-email-przanoni@gmail.com> References: <1366313746-3659-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-qc0-f178.google.com (mail-qc0-f178.google.com [209.85.216.178]) by gabe.freedesktop.org (Postfix) with ESMTP id E6EEDE65A2 for ; Thu, 18 Apr 2013 12:36:49 -0700 (PDT) Received: by mail-qc0-f178.google.com with SMTP id d10so1584644qca.9 for ; Thu, 18 Apr 2013 12:36:49 -0700 (PDT) In-Reply-To: <1366313746-3659-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni This should replace intel_using_power_well. The idea is that we're adding the requested power domain as an argument, so this might enable the code to look less platform-specific and also allows us to easily add new domains in case we need. Requested-by: Daniel Vetter Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_display.c | 16 +++++++++++----- drivers/gpu/drm/i915/intel_drv.h | 10 +++++++++- drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++++----- 3 files changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b86023d..b492eaa 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1227,8 +1227,8 @@ void assert_pipe(struct drm_i915_private *dev_priv, if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) state = true; - if (!intel_using_power_well(dev_priv->dev) && - cpu_transcoder != TRANSCODER_EDP) { + if (cpu_transcoder != TRANSCODER_EDP && + !intel_display_power_enabled(dev_priv->dev, POWER_DOMAIN_OTHER)) { cur_state = false; } else { reg = PIPECONF(cpu_transcoder); @@ -3584,6 +3584,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) int pipe = intel_crtc->pipe; int plane = intel_crtc->plane; enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; + enum intel_display_power_domain domain; if (!intel_crtc->active) return; @@ -3607,7 +3608,12 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) /* XXX: Once we have proper panel fitter state tracking implemented with * hardware state read/check support we should switch to only disable * the panel fitter when we know it's used. */ - if (intel_using_power_well(dev)) { + if (pipe == PIPE_A) + domain = POWER_DOMAIN_PIPE_A_PANEL_FITTER; + else + domain = POWER_DOMAIN_OTHER; + + if (intel_display_power_enabled(dev, domain)) { I915_WRITE(PF_CTL(pipe), 0); I915_WRITE(PF_WIN_SZ(pipe), 0); } @@ -5859,8 +5865,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; uint32_t tmp; - if (!intel_using_power_well(dev_priv->dev) && - cpu_transcoder != TRANSCODER_EDP) + if (cpu_transcoder != TRANSCODER_EDP && + !intel_display_power_enabled(dev, POWER_DOMAIN_OTHER)) return false; tmp = I915_READ(PIPECONF(cpu_transcoder)); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index b5b6d19..04b3f84 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -465,6 +465,13 @@ struct intel_fbc_work { int interval; }; +enum intel_display_power_domain { + POWER_DOMAIN_PIPE_A, + POWER_DOMAIN_PIPE_A_PANEL_FITTER, + POWER_DOMAIN_TRANSCODER_EDP, + POWER_DOMAIN_OTHER, +}; + int intel_pch_rawclk(struct drm_device *dev); int intel_connector_update_modes(struct drm_connector *connector, @@ -700,7 +707,8 @@ extern void intel_update_fbc(struct drm_device *dev); extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); extern void intel_gpu_ips_teardown(void); -extern bool intel_using_power_well(struct drm_device *dev); +extern bool intel_display_power_enabled(struct drm_device *dev, + enum intel_display_power_domain domain); extern void intel_init_power_well(struct drm_device *dev); extern void intel_set_power_well(struct drm_device *dev, bool enable); extern void intel_enable_gt_powersave(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 2557926..1c472d7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4287,15 +4287,28 @@ void intel_init_clock_gating(struct drm_device *dev) * enable it, so check if it's enabled and also check if we've requested it to * be enabled. */ -bool intel_using_power_well(struct drm_device *dev) +bool intel_display_power_enabled(struct drm_device *dev, + enum intel_display_power_domain domain) { struct drm_i915_private *dev_priv = dev->dev_private; + bool power_well_enabled; - if (IS_HASWELL(dev)) - return I915_READ(HSW_PWR_WELL_DRIVER) == - (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE); - else + if (!HAS_POWER_WELL(dev)) + return true; + + power_well_enabled = I915_READ(HSW_PWR_WELL_DRIVER) == + (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE); + + switch (domain) { + case POWER_DOMAIN_PIPE_A: + case POWER_DOMAIN_TRANSCODER_EDP: return true; + case POWER_DOMAIN_PIPE_A_PANEL_FITTER: + case POWER_DOMAIN_OTHER: + return power_well_enabled; + default: + BUG(); + } } void intel_set_power_well(struct drm_device *dev, bool enable) -- 1.7.10.4