From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: [PATCH 3/4] drm/i915: set proper DPIO post divider for VGA on VLV v4 Date: Thu, 2 May 2013 10:48:09 -0700 Message-ID: <1367516890-3469-3-git-send-email-jbarnes@virtuousgeek.org> References: <1367516890-3469-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy7-pub.bluehost.com (oproxy7-pub.bluehost.com [67.222.55.9]) by gabe.freedesktop.org (Postfix) with SMTP id DBF4FE5C65 for ; Thu, 2 May 2013 10:48:14 -0700 (PDT) Received: from [67.161.37.189] (port=42257 helo=localhost.localdomain) by box514.bluehost.com with esmtpsa (TLSv1:CAMELLIA256-SHA:256) (Exim 4.80) (envelope-from ) id 1UXxc6-0003hM-C1 for intel-gfx@lists.freedesktop.org; Thu, 02 May 2013 11:48:14 -0600 In-Reply-To: <1367516890-3469-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org Supposedly we should use the DAC divider for <300MHz pixel clocks, but as that doesn't actually work as well as the high freq divider here in practice, just use the high freq divider all the time. v2: remove unconditional write (Jesse) check for pixel rate properly (Jesse) v3: give up, the DAC divider apparently doesn't work, and low res modes work ok (Jesse) remove debug msg (Jesse) Signed-off-by: Jesse Barnes --- drivers/gpu/drm/i915/intel_display.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 6504337..59c2114 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4425,10 +4425,13 @@ static void vlv_update_pll(struct intel_crtc *crtc) mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); mdiv |= ((bestn << DPIO_N_SHIFT)); mdiv |= (1 << DPIO_K_SHIFT); - if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) || - intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || - intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) - mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); + + /* + * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, + * but we don't support that). + * Note: don't use the DAC post divider as it seems unstable. + */ + mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); mdiv |= DPIO_ENABLE_CALIBRATION; -- 1.7.10.4