From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paulo Zanoni Subject: [PATCH 3/5] drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state Date: Fri, 3 May 2013 12:15:38 -0300 Message-ID: <1367594140-4339-3-git-send-email-przanoni@gmail.com> References: <1367594140-4339-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-vc0-f170.google.com (mail-vc0-f170.google.com [209.85.220.170]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FBADE5DFD for ; Fri, 3 May 2013 08:16:08 -0700 (PDT) Received: by mail-vc0-f170.google.com with SMTP id gf12so1524452vcb.15 for ; Fri, 03 May 2013 08:16:08 -0700 (PDT) In-Reply-To: <1367594140-4339-1-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org From: Paulo Zanoni In the error state function we read the registers without checking if the power well is on, so after doing this we have to clear the FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting it and printing an error message. The first version of this patch was checking for the power well state and then avoiding reading registers that were off, but the reviewers requested to just read the registers any way and then later clear the FPGA_DBG_RM_NOCLAIM bit. Signed-off-by: Paulo Zanoni Reviewed-by: Damien Lespiau --- drivers/gpu/drm/i915/intel_display.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 190b787..fcb1367 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9826,6 +9826,13 @@ intel_display_capture_error_state(struct drm_device *dev) error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); } + /* In the code above we read the registers without checking if the power + * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to + * prevent the next I915_WRITE from detecting it and printing an error + * message. */ + if (HAS_POWER_WELL(dev)) + I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); + return error; } -- 1.7.10.4